PIC24HJ128GP510-I/PT Microchip Technology Inc., PIC24HJ128GP510-I/PT Datasheet - Page 151
PIC24HJ128GP510-I/PT
Manufacturer Part Number
PIC24HJ128GP510-I/PT
Description
MCU, 16-Bit, 128KB Flash, 8KB RAM, 85 I/O, TQFP-100
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC24HJ128GP510-IPT.pdf
(286 pages)
Specifications of PIC24HJ128GP510-I/PT
A/d Inputs
32 Channel, 12-Bit
Cpu Speed
40 MIPS
Eeprom Memory
0 Bytes
Input Output
85
Interface
CAN/I2C/SPI/UART
Memory Type
Flash
Number Of Bits
16
Number Of Inputs
85
Number Of Pins
100
Package Type
100-pin TQFP
Programmable Memory
128K Bytes
Ram Size
8K Bytes
Speed
40 MIPS
Timers
9-16-bit, 4-32-bit
Voltage, Range
3-3.6 V
Voltage, Rating
3-3.6 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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REGISTER 15-1:
© 2007 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-7
bit 6
bit 5-2
bit 1
bit 0
SPIEN
R/W-0
U-0
—
SPIEN: SPIx Enable bit
1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables module
Unimplemented: Read as ‘0’
SPISIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
Unimplemented: Read as ‘0’
SPIROV: Receive Overflow Flag bit
1 = A new byte/word is completely received and discarded. The user software has not read the
0 = No overflow has occurred
Unimplemented: Read as ‘0’
SPITBF: SPIx Transmit Buffer Full Status bit
1 = Transmit not yet started, SPIxTXB is full
0 = Transmit started, SPIxTXB is empty
Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB.
Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.
SPIRBF: SPIx Receive Buffer Full Status bit
1 = Receive complete, SPIxRXB is full
0 = Receive is not complete, SPIxRXB is empty
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB.
Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB.
SPIROV
R/C-0
previous data in the SPIxBUF register.
U-0
—
SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
SPISIDL
R/W-0
U-0
—
PIC24HJXXXGPX06/X08/X10
U-0
U-0
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
—
—
U-0
U-0
—
—
x = Bit is unknown
SPITBF
U-0
R-0
—
DS70175F-page 149
SPIRBF
U-0
R-0
—
bit 8
bit 0
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