PIC24HJ128GP510-I/PT Microchip Technology Inc., PIC24HJ128GP510-I/PT Datasheet - Page 89

• Manufacturer Part Number: PIC24HJ128GP510-I/PT
• Description: MCU, 16-Bit, 128KB Flash, 8KB RAM, 85 I/O, TQFP-100
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24HJ128GP510-I/PT

• A/d Inputs: 32 Channel, 12-Bit
• Cpu Speed: 40 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 85
• Interface: CAN/I2C/SPI/UART
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Inputs: 85
• Number Of Pins: 100
• Package Type: 100-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 8K Bytes
• Speed: 40 MIPS
• Timers: 9-16-bit, 4-32-bit
• Voltage, Range: 3-3.6 V
• Voltage, Rating: 3-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

REGISTER 6-13:
© 2007 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12-9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
C2RXIE
R/W-0
U-0
—
Unimplemented: Read as ‘0’
DMA5IE: DMA Channel 5 Data Transfer Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Unimplemented: Read as ‘0’
C2IE: ECAN2 Event Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
C2RXIE: ECAN2 Receive Data Ready Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
INT4IE: External Interrupt 4 Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
INT3IE: External Interrupt 3 Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
T9IE: Timer9 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
T8IE: Timer8 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
MI2C2IE: I2C2 Master Events Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
SI2C2IE: I2C2 Slave Events Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
T7IE: Timer7 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
INT4IE
R/W-0
U-0
—
IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
W = Writable bit
‘1’ = Bit is set
DMA5IE
INT3IE
R/W-0
R/W-0
PIC24HJXXXGPX06/X08/X10
R/W-0
T9IE
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
T8IE
U-0
—
MI2C2IE
R/W-0
U-0
—
x = Bit is unknown
SI2C2IE
R/W-0
U-0
—
DS70175F-page 87
R/W-0
R/W-0
C2IE
T7IE
bit 8
bit 0