PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 172

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
REGISTER 10-18: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5
DS39977C-page 172
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W-1
IRXIP
IRXIP: Invalid Message Received Interrupt Priority bits
1 = High priority
0 = Low priority
WAKIP: Bus Wake Up Activity Interrupt Priority bit
1 = High priority
0 = Low priority
1 = High priority
0 = Low priority
TXB2IP: Transmit Buffer 2 Interrupt Priority bit
1 = High priority
0 = Low priority
TXB1IP: Transmit Buffer 1 Interrupt Priority bit
1 = High priority
0 = Low priority
TXB0IP: Transmit Buffer 0 Interrupt Priority bit
1 = High priority
0 = Low priority
RXB1IP: Receive Buffer 1 Interrupt Priority bit
Mode 0:
1 = High priority for Receive Buffer 1
0 = Low priority for Receive Buffer 1
Modes 1 and 2:
1 = High priority for received messages
0 = Low priority for received messages
RXB0IP/FIFOFIP: Receive Buffer 0 Interrupt Priority bit
Mode 0:
1 = High priority for Receive Buffer 0
0 = Low priority for Receive Buffer 0
Mode 1:
Unimplemented: Read as ‘ 0 ’
Mode 2:
FIFOFIE: FIFO Full Interrupt Flag bit
1 = High priority
0 = Low priority
ERRIP: CAN Bus Error Interrupt Priority bit
WAKIP
R/W-1
W = Writable bit
‘1’ = Bit is set
ERRIP
R/W-1
TXB2IP
R/W-1
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TXB1IP
R/W-1
TXB0IP
R/W-1
 2011 Microchip Technology Inc.
x = Bit is unknown
RXB1IP
R/W-1
RXB0IP/
FIFOFIE
R/W-1
bit 0