PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 222

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18F66K80 FAMILY
14.7
If ECCP modules are configured to use Timer1 and to
generate a Special Event Trigger in Compare mode
(CCP1M<3:0> = 1011 ), this signal will reset Timer1. The
trigger from ECCP will also start an A/D conversion if the
A/D module is enabled. (For more information, see
Section 20.3.4 “Special Event Trigger”
To take advantage of this feature, the module must be
configured as either a timer or a synchronous counter.
When used this way, the CCPR1H:CCPR1L register
pair effectively becomes a Period register for Timer1.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
Special Event Trigger, the write operation will take
precedence.
DS39977C-page 222
Note:
Resetting Timer1 Using the ECCP
Special Event Trigger
The Special Event Trigger from the ECCP
module will only clear the TMR1 register’s
content, but not set the TMR1IF interrupt
flag bit (PIR1<0>).
.)
Preliminary
14.8
Timer1 can be configured to count freely or the count can
be enabled and disabled using the Timer1 gate circuitry.
This is also referred to as Timer1 gate count enable.
Timer1 gate can also be driven by multiple selectable
sources.
14.8.1
The Timer1 Gate Enable mode is enabled by setting
the TMR1GE bit of the T1GCON register. The polarity
of the Timer1 Gate Enable mode is configured using
the T1GPOL bit (T1GCON<6>).
When Timer1 Gate Enable mode is enabled, Timer1
will increment on the rising edge of the Timer1 clock
source. When Timer1 Gate Enable mode is disabled,
no incrementing will occur and Timer1 will hold the
current count. See
TABLE 14-3:
† The clock on which TMR1 is running. For more
T1CLK
Note:
information, see




(†)
Timer1 Gate
TIMER1 GATE COUNT ENABLE
The CCP and ECCP modules use Timers,
1 through 4, for some modes. The assign-
ment of a particular timer to a CCP/ECCP
module is determined by the Timer to CCP
enable bits in the CCPTMRS register. For
more details, see
Register
(T1GCON<6>)
T1GPOL
TIMER1 GATE ENABLE
SELECTIONS
0
0
1
1
Figure 14-4
Figure
19-2.
 2011 Microchip Technology Inc.
14-1.
T1G Pin
for timing details.
0
1
0
1
Register 20-2
Counts
Holds Count
Holds Count
Counts
Operation
Timer1
and