PIC18F26K80-E/SP Microchip Technology Inc., PIC18F26K80-E/SP Datasheet - Page 65

• Manufacturer Part Number: PIC18F26K80-E/SP
• Description: 28 SPDIP .300IN TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F26K80-E/SP

• A/d Inputs: 8-Channel, 12-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 64K Bytes
• Ram Size: 3.6K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

3.8
When PRI_IDLE mode is selected, the designated pri-
mary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin if used by the oscillator) will stop oscillating.
In
SEC_IDLE), the SOSC oscillator is operating and
providing the device clock. The SOSC oscillator may
also run in all power-managed modes if required to
clock SOSC.
In RC_RUN and RC_IDLE modes, the internal
oscillator provides the device clock source. The 31 kHz
LF-INTOSC output can be used directly to provide the
clock and may be enabled to support various special
features, regardless of the power-managed mode (see
Section 28.2 “Watchdog Timer (WDT)”
Section 28.5 “Fail-Safe Clock Monitor”
information on WDT, Fail-Safe Clock Monitor and
Two-Speed Start-up).
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTOSC is required to support WDT operation. The
SOSC oscillator may be operating to support Timer1 or
3. Other features may be operating that do not require a
device clock source (i.e., MSSP slave, INTx pins and
others). Peripherals that may add significant current
consumption are listed in
istics:
PIC18F66K80 Family
TABLE 3-4:
 2011 Microchip Technology Inc.
EC, ECPLL
HS, HSPLL
INTOSC, INTPLL1/2
Note:
secondary
Oscillator Mode
Effects of Power-Managed Modes
on the Various Clock Sources
Power-Down
See
Section 5.0 “Reset”
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
clock
(Industrial/Extended)”.
Section 31.2 “DC Character-
modes
and
Floating, pulled by external clock
Feedback inverter disabled at quiescent
voltage level
I/O pin, RA6, direction controlled by
TRISA<6>
Supply
(SEC_RUN
for time-outs due to Sleep and MCLR Reset.
for more
OSC1 Pin
Current
through
and
Preliminary
PIC18F66K80 FAMILY
3.9
Power-up delays are controlled by two timers, so that
no external Reset circuitry is required for most applica-
tions. The delays ensure that the device is kept in
Reset until the device power supply is stable under nor-
mal circumstances and the primary clock is operating
and stable. For additional information on power-up
delays,
(PWRT)”.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up time of about 64 ms
(Parameter 33,
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (HS, XT or LP modes). The
OST does this by counting 1,024 oscillator cycles
before allowing the oscillator to clock the device.
There is a delay of interval, T
Table
becomes ready to execute instructions.
31-11), following POR, while the controller
Power-up Delays
see
At logic low (clock/4 output)
Feedback inverter disabled at quiescent
voltage level
I/O pin, RA6, direction controlled by
TRISA<7>
Table
Section 5.6.1
31-11); it is always enabled.
OSC2 Pin
CSD
“Power-up
DS39977C-page 65
(Parameter 38,
Timer