PIC24FJ128DA110-I/PT Microchip Technology Inc., PIC24FJ128DA110-I/PT Datasheet - Page 247

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PIC24FJ128DA110-I/PT

Manufacturer Part Number
PIC24FJ128DA110-I/PT
Description
100 TQFP 12x12x1mm TRAY, 16-bit, 128KB Flash, 24K RAM, USB, Graphics
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC24FJ128DA110-I/PT

A/d Inputs
24 Channel, 10-bit
Comparators
3
Cpu Speed
16 MIPS
Eeprom Memory
0 Bytes
Input Output
84
Interface
I2C/SPI/UART/USART/USB
Memory Type
Flash
Number Of Bits
16
Package Type
100-pin TQFP
Programmable Memory
128K Bytes
Ram Size
24K Bytes
Speed
32 MHz
Temperature Range
–40 to 85 °C
Timers
5-16-bit
Voltage, Range
2.2-3.6 V
Lead Free Status / Rohs Status
RoHS Compliant part

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24FJ128DA110-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
REGISTER 18-2:
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-12
bit 11
bit 10
bit 9-0
Note 1:
R/W-x, HSC
UOWN
R/W-x
BC7
This bit is ignored unless DTSEN = 1.
UOWN: USB Own bit
0 = The microcontroller core owns the BD and its corresponding buffer; the USB module ignores all
DTS: Data Toggle Packet bit
1 = Data 1 packet
0 = Data 0 packet
Reserved: Maintain as ‘0’
DTSEN: Data Toggle Synchronization Enable bit
1 = Data toggle synchronization is enabled; data packets with incorrect sync value will be ignored
0 = No data toggle synchronization is performed
BSTALL: Buffer Stall Enable bit
1 = Buffer STALL enabled; STALL handshake issued if a token is received that would use the BD in
0 = Buffer STALL disabled
BC<9:0>: Byte Count bits
This represents the number of bytes to be transmitted or the maximum number of bytes to be received
during a transfer. Upon completion, the byte count is updated by the USB module with the actual
number of bytes transmitted or received.
R/W-x, HSC
DTS
R/W-x
BC6
other fields in the BD
the given location (UOWN bit remains set, BD value is unchanged); corresponding EPSTALL bit
will get set on any STALL handshake
BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER PROTOTYPE, CPU
MODE (BD0STAT THROUGH BD63STAT)
(1)
HSC = Hardware Settable/Clearable bit
W = Writable bit
‘1’ = Bit is set
R/W-x, HSC
Reserved
BC5
r-0
(1)
R/W-x, HSC
Reserved
PIC24FJ256DA210 FAMILY
BC4
r-0
U = Unimplemented bit, read as ‘0’
‘r’ = Reserved bit
R/W-x, HSC
DTSEN
R/W-x
BC3
R/W-x, HSC
BSTALL
R/W-x
BC2
r = Reserved bit
x = Bit is unknown
R/W-x, HSC
R/W-x, HSC
BC9
BC1
DS39969B-page 247
R/W-x, HSC
R/W-x, HSC
BC8
BC0
bit 8
bit 0

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