PIC24FJ128DA110-I/PT Microchip Technology Inc., PIC24FJ128DA110-I/PT Datasheet - Page 35

• Manufacturer Part Number: PIC24FJ128DA110-I/PT
• Description: 100 TQFP 12x12x1mm TRAY, 16-bit, 128KB Flash, 24K RAM, USB, Graphics
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ128DA110-I/PT

• A/d Inputs: 24 Channel, 10-bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 84
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 100-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 24K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part

2.4
The on-chip voltage regulator enable/disable pin
(ENVREG or DISVREG, depending on the device
family) must always be connected directly to either a
supply voltage or to ground. The particular connection
is determined by whether or not the regulator is to be
used:
• For ENVREG, tie to V
• For DISVREG, tie to ground to enable the
Refer to Section 27.2 “On-Chip Voltage Regulator”
for details on connecting and using the on-chip
regulator.
When the regulator is enabled, a low-ESR (<5Ω)
capacitor is required on the V
stabilize the voltage regulator output voltage. The
V
must use a capacitor of 10 F connected to ground. The
type can be ceramic or tantalum. A suitable example is
the Murata GRM21BF50J106ZE01 (10 F, 6.3V) or
equivalent. Designers may use Figure 2-3 to evaluate
ESR equivalence of candidate devices.
The placement of this capacitor should be close to
V
length not exceed 0.25 inch (6 mm). Refer to
Section 30.0
additional information.
When the regulator is disabled, the V
must be tied to a voltage supply at the V
Refer to Section 30.0 “Electrical Characteristics” for
information on V
 2010 Microchip Technology Inc.
CAP
CAP
Note:
or to ground to disable the regulator
regulator or to V
/V
/V
DDCORE
DDCORE
Voltage Regulator Pins
(ENVREG/DISVREG and
V
CAP
This section applies only to PIC24FJ
devices with an on-chip voltage regulator.
. It is recommended that the trace
/V
pin must not be connected to V
“Electrical
DD
DDCORE
DD
and V
to disable the regulator
DD
DDCORE
to enable the regulator,
)
Characteristics”
CAP
.
/V
CAP
DDCORE
DDCORE
/V
DDCORE
DD
PIC24FJ256DA210 FAMILY
pin to
level.
, and
pin
for
FIGURE 2-3:
2.5
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming (ICSP) and debugging purposes.
It is recommended to keep the trace length between
the ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recom-
mended, with the value in the range of a few tens of
ohms, not to exceed 100Ω.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communi-
cations to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(V
For device emulation, ensure that the “Communication
Channel Select” (i.e., PGECx/PGEDx pins) programmed
into the device matches the physical connections for the
ICSP to the Microchip debugger/emulator tool.
For
development tools connection requirements, refer to
Section 28.0 “Development Support”.
IH
0.001
Note:
0.01
) and input low (V
0.1
10
more
1
0.01
ICSP Pins
Data for Murata GRM21BF50J106ZE01 shown.
Measurements at 25°C, 0V DC bias.
information
0.1
Frequency (MHz)
IL
FREQUENCY vs. ESR
PERFORMANCE FOR
SUGGESTED V
1
) requirements.
on
10
available
100
DS39969B-page 35
CAP
1000 10,000
Microchip