PIC24FJ128DA110-I/PT Microchip Technology Inc., PIC24FJ128DA110-I/PT Datasheet - Page 91

• Manufacturer Part Number: PIC24FJ128DA110-I/PT
• Description: 100 TQFP 12x12x1mm TRAY, 16-bit, 128KB Flash, 24K RAM, USB, Graphics
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ128DA110-I/PT

• A/d Inputs: 24 Channel, 10-bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 84
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 100-pin TQFP
• Programmable Memory: 128K Bytes
• Ram Size: 24K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part

TABLE 6-3:
6.3.1
The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) will have a relatively long
start-up time. Therefore, one or more of the following
conditions is possible after SYSRST is released:
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has not expired (if a
• The PLL has not achieved a lock (if PLL is used).
The device will not begin to execute code until a valid
clock source has been released to the system. There-
fore, the oscillator and PLL start-up delays must be
considered when the Reset delay time must be known.
 2010 Microchip Technology Inc.
POR
BOR
MCLR
WDT
Software
Illegal Opcode
Uninitialized W
Trap Conflict
Note 1:
crystal oscillator is used).
Reset Type
(7)
2:
3:
4:
5:
6:
7:
T
T
WUTSEL<1:0> bits setting).
T
T
oscillator clock to the system.
T
T
If Two-speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC
so the system clock delay is just T
primary oscillator after its respective clock delay.
POR AND LONG OSCILLATOR
START-UP TIMES
STARTUP
OST
RST
POR
LOCK
FRC
= Internal State Reset time (32 s nominal).
= Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the
and T
= Power-on Reset delay (10 s nominal).
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
= PLL lock time.
EC
ECPLL
XT, HS, SOSC
XTPLL, HSPLL
FRC, FRCDIV
FRCPLL
LPRC
EC
ECPLL
XT, HS, SOSC
XTPLL, HSPLL
FRC, FRCDIV
FRCPLL
LPRC
Any Clock
Any Clock
Any clock
Any Clock
Any Clock
Any Clock
= T
LPRC
VREG
Clock Source
= RC Oscillator start-up times.
(10 s nominal when VREGS = 1 and when VREGS = 0; depends upon
FRC
PIC24FJ256DA210 FAMILY
, and in such cases, FRC start-up time is valid. It switches to the
T
T
T
T
T
T
T
POR
POR
POR
POR
POR
POR
POR
T
T
T
T
T
T
T
SYSRST Delay
STARTUP
STARTUP
STARTUP
STARTUP
STARTUP
STARTUP
STARTUP
+ T
+ T
+ T
+ T
+ T
+ T
+ T
STARTUP
STARTUP
STARTUP
STARTUP
STARTUP
STARTUP
STARTUP
T
T
T
T
T
T
6.3.2
If the FSCM is enabled, it will begin to monitor the
system clock source when SYSRST is released. If a
valid clock source is not available at this time, the
device will automatically switch to the FRC oscillator
and the user can switch to the desired crystal oscillator
in the Trap Service Routine (TSR).
RST
RST
RST
RST
RST
RST
+ T
+ T
+ T
+ T
+ T
+ T
+ T
RST
RST
RST
RST
RST
RST
RST
+ T
+ T
+ T
+ T
+ T
+ T
+ T
RST
RST
RST
RST
RST
RST
RST
FAIL-SAFE CLOCK MONITOR
(FSCM) AND DEVICE RESETS
System Clock
T
T
T
T
OST
OST
FRC
FRC
T
T
Delay
T
T
T
T
T
T
LOCK
LPRC
LOCK
LPRC
OST
+ T
OST
+ T
FRC
+ T
FRC
+ T
—
—
—
—
—
—
—
—
LOCK
LOCK
LOCK
LOCK
DS39969B-page 91
1, 2, 3
1, 2, 3, 5
1, 2, 3, 4
1, 2, 3, 4, 5
1, 2, 3, 6, 7
1, 2, 3, 5, 6
1, 2, 3, 6
2, 3
2, 3, 5
2, 3, 4
2, 3, 4, 5
2, 3, 6, 7
2, 3, 5, 6
2, 3, 6
3
3
3
3
3
3
Notes