PIC16F1947-I/PT Microchip Technology Inc., PIC16F1947-I/PT Datasheet - Page 287

• Manufacturer Part Number: PIC16F1947-I/PT
• Description: 64 TQFP 10x10x1mm TRAY28KB Flash, 1KB RAM, 256B EEPROM, LCD, 1.8-5.5V
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1947-I/PT

• A/d Inputs: 17-Channel, 10-Bit
• Comparators: 3
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 54
• Interface: CAN/I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 28K Bytes
• Ram Size: 1K Bytes
• Speed: 32 MHz
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

24.6.13.2
During a Repeated Start condition, a bus collision
occurs if:
a)
b)
When the user releases SDAx and the pin is allowed to
float high, the BRG is loaded with SSPxADD and
counts down to zero. The SCLx pin is then deasserted
and when sampled high, the SDAx pin is sampled.
FIGURE 24-36:
FIGURE 24-37:
 2010 Microchip Technology Inc.
A low level is sampled on SDAx when SCLx
goes from low level to high level.
SCLx goes low before SDAx is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
SDAx
SCLx
BCLxIF
RSEN
S
SSPxIF
SDAx
SCLx
RSEN
BCLxIF
S
SSPxIF
Bus Collision During a Repeated
Start Condition
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SCLx goes low before SDAx,
set BCLxIF. Release SDAx and SCLx.
Preliminary
T
BRG
Sample SDAx when SCLx goes high.
If SDAx = 0, set BCLxIF and release SDAx and SCLx.
If SDAx is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’,
If SDAx is sampled high, the BRG is reloaded and
begins counting. If SDAx goes from high-to-low before
the BRG times out, no bus collision occurs because no
two masters can assert SDAx at exactly the same time.
If SCLx goes from high-to-low before the BRG times
out and SDAx has not already been asserted, a bus
collision occurs. In this case, another master is
attempting to transmit a data ‘1’ during the Repeated
Start condition, see
If, at the end of the BRG time-out, both SCLx and SDAx
are still high, the SDAx pin is driven low and the BRG
is reloaded and begins counting. At the end of the
count, regardless of the status of the SCLx pin, the
SCLx pin is driven low and the Repeated Start
condition is complete.
PIC16F/LF1946/47
Figure
T
Cleared by software
BRG
24-36.
Interrupt cleared
by software
’0’
’0’
DS41414B-page 287
’0’
Figure
24-35).