PIC16F1947-I/PT Microchip Technology Inc., PIC16F1947-I/PT Datasheet - Page 40
PIC16F1947-I/PT
Manufacturer Part Number
PIC16F1947-I/PT
Description
64 TQFP 10x10x1mm TRAY28KB Flash, 1KB RAM, 256B EEPROM, LCD, 1.8-5.5V
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16LF1946-IPT.pdf
(448 pages)
Specifications of PIC16F1947-I/PT
A/d Inputs
17-Channel, 10-Bit
Comparators
3
Cpu Speed
8 MIPS
Eeprom Memory
256 Bytes
Input Output
54
Interface
CAN/I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
64-pin TQFP
Programmable Memory
28K Bytes
Ram Size
1K Bytes
Speed
32 MHz
Timers
4-8-bit, 1-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC16F1947-I/PT
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PIC16F1947-I/PT
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PIC16F1947-I/PT
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PIC16F/LF1946/47
TABLE 3-9:
DS41414B-page 40
380h
381h
382h
383h
384h
385h
386h
387h
388h
389h
38Ah
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
39Fh
Legend:
Note 1:
Address
Bank 7
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1, 2)
(2)
2:
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
LATF
LATG
—
—
—
—
—
—
IOCBP
IOCBN
IOCBF
—
—
—
—
—
—
—
—
—
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred
to the upper byte of the program counter.
These registers can be addressed from any bank.
Name
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
Working Register
PORTF Data Latch
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
IOCBP7
IOCBN7
IOCBF7
Bit 7
GIE
—
—
—
—
Write Buffer for the upper 7 bits of the Program Counter
IOCBN6
IOCBP6
IOCBF6
Bit 6
PEIE
—
—
—
IOCBN5
TMR0IE
IOCBP5
IOCBF5
LATG5
Bit 5
—
—
Preliminary
IOCBP4
IOCBN4
IOCBF4
LATG4
INTE
Bit 4
TO
IOCBN3
IOCBP3
IOCBF3
LATG3
IOCIE
Bit 3
PD
BSR<4:0>
IOCBN2
TMR0IF
IOCBP2
IOCBF2
LATG2
Bit 2
Z
IOCBP1
IOCBN1
IOCBF1
LATG1
INTF
Bit 1
DC
2010 Microchip Technology Inc.
IOCBP0
IOCBN0
IOCBF0
LATG0
IOCIF
Bit 0
C
xxxx xxxx xxxx xxxx
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
--xx xxxx --uu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
POR, BOR
Value on:
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Value on all
Resets
other
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
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