PAC-POWR1220AT8-HS-EVN Lattice, PAC-POWR1220AT8-HS-EVN Datasheet - Page 38

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PAC-POWR1220AT8-HS-EVN

Manufacturer Part Number
PAC-POWR1220AT8-HS-EVN
Description
Supervisory Circuits Pwr Mgr Hercules Std Development Kit
Manufacturer
Lattice
Series
ispPAC®, MachXO, Herculesr

Specifications of PAC-POWR1220AT8-HS-EVN

Silicon Manufacturer
Lattice Semiconductor
Kit Application Type
Power Management
Application Sub Type
Power Manager
Kit Contents
Preloaded Board, Eval Board, AC Adapter, USB Connector Cable
Rohs Compliant
Yes
Main Purpose
Power Management, ORing Controller / Hot Swap Controller
Embedded
Yes, Other
Utilized Ic / Part
ispPAC-POWR1220AT8, LCMXO2280
Primary Attributes
-
Secondary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Lattice Semiconductor
Figure 1-28. I
The I
issuing a write of any value to the I
is equivalent to toggling the Resetb pin of the chip. Refer to the Resetb Signal, RESET Command via JTAG or I
section of this data sheet for further information.
Figure 1-29. I
2
C interface also provides the ability to initiate reset operations. The ispPAC-POWR1220AT8 may be reset by
2
2
C Register Mapping for UES Bits
C Reset Register
0x12 - RESET (Write Only)
0x0A - UES_BYTE0 (Read Only)
0x0B - UES_BYTE1 (Read Only)
0x0C - UES_BYTE2 (Read Only)
0x0D - UES_BYTE3 (Read Only)
UES15
UES23
UES31
UES7
b7
b7
b7
b7
b7
X
UES14
UES22
UES30
UES6
b6
b6
b6
b6
b6
X
2
C RESET register (Figure 1-29). Note: The execution of the I
UES13
UES21
UES29
UES5
b5
b5
b5
b5
b5
X
UES12
UES20
UES28
UES4
b4
b4
b4
b4
b4
X
1-38
UES11
UES19
UES27
UES3
b3
b3
b3
b3
b3
X
UES10
UES18
UES26
ispPAC-POWR1220AT8 Data Sheet
UES2
b2
b2
b2
b2
b2
X
UES17
UES25
UES1
UES9
b1
b1
b1
b1
b1
X
UES16
UES24
UES0
UES8
b0
b0
b0
b0
b0
X
2
C reset command
2
C

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