PEB24901HV1.2 Lantiq, PEB24901HV1.2 Datasheet - Page 31

• Manufacturer Part Number: PEB24901HV1.2
• Manufacturer: Lantiq

Specifications of PEB24901HV1.2

• Lead Free Status / Rohs Status: Supplier Unconfirmed

PEB 24901
EXTEST is used to examine the board interconnections.
When the TAP controller is in the state "update DR", all output pins are updated with the
falling edge of TCK. When it has entered state "capture DR" the levels of all input pins
are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically
done using the instruction SAMPLE/PRELOAD.
INTEST supports internal chip testing.
When the TAP controller is in the state "update DR", all inputs are updated internally with
the falling edge of TCK. When it has entered state "capture DR" the levels of all outputs
are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically
done using the instruction SAMPLE/PRELOAD.
Note: 0001 (INTEST) is the default value of the instruction register.
SAMPLE/PRELOAD provides a snap-shot of the pin level during normal operation or is
used to preload (TDI) / shift out (TDO) the boundary scan with a test vector. Both
activities are transparent to the system functionality.
IDCODE Register
The 32-bit identification register is serially read out via TDO. It contains the version
number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). The LSB
is fixed to "1".
Version
Device Code
Manufacturer Code
Output
0001
0000 0000 0010 1010
0000 1000 001
1
-->
TDO
Note:In the state "test logic reset" the code "0011" is loaded into the instruction code
register.
BYPASS, a bit entering TDI is shifted to TDO after one TCK clock cycle, e.g. to skip
testing of selected ICs on a printed circuit board.
SSP does the same as setting the pins TSP and RESQ in SSP-mode. Single alternating
pulses are issued to the Quad IEC AFE on all ports via the SDX pin.
Semiconductor Group
30
02.95