MC145574APBR2 Freescale Semiconductor, MC145574APBR2 Datasheet - Page 53

• Manufacturer Part Number: MC145574APBR2
• Manufacturer: Freescale Semiconductor

Specifications of MC145574APBR2

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
6.6
6.7
In the GCI NT master mode, it is possible to select both NT1 Star and NT Terminal modes via the
Monitor channel. The associated pins used in the default IDL2 mode are enabled and operate in the
same manner.
In the GCI TE master mode, only three modes of operation are available.
When M(2:0) = 4, terminal mode is selected. In this mode, the MC145574 always operates in channel 0,
and D channel availability is indicated in two ways:
2B+D CHANNELS
In the activated state, GCI transparently transmits the information in the B and D channels in the NT
and TE slave modes. In TE master mode, D channel flow control is operational and access to the
D channel must be requested. Refer to the section on GCI D channel operation for further details.
M AND A/E CHANNELS
The GCI M (or Monitor) channel is intended to be used for the transfer of operation and maintenance
information between management and layer 1 entities. For the MC145574, this means that the Monitor
channel is used to access the internal registers defined for the SCP mode of operation. The A/E channel
is used to control the transfer of the information on the Monitor channel by providing a handshake
facility.
1. If pin SG = 1, then the D channel is currently idle and available for access. If pin SG = 0, then
2. In parallel with the SG pin, this signal is also output from the device in bit 4 of the C/I channel
the D channel on the passive bus is being used by another TE device.
If the SG pin toggles during the time when the device is using the D channel, then a collision
has occurred and the device stops its D channel access. SG indicates stop/go for D channel
access.
of CH2. This is compatible with the SCIT bus specification and is also compatible with the
MC68302. This is enabled via the Monitor channel in register OR7(6).
When M(2:0) = 7, only one GCI channel is available, and D channel availability is indicated by
the SG pin only.
The D channel access circuitry can be disabled by writing to a control register via the Monitor
channel, BR7(6). When this is done, it is assumed that the device is not operating in a passive
bus application and has sole use of the D channel. When disabled, the SG pin and bit always
equal one, and the GCI D channel data flows transparently to the S/T loop interface.
Freescale Semiconductor, Inc.
Table 6–4. M2, M1, and M0 Pins in GCI TE Master Mode
M2
For More Information On This Product,
0
0
0
0
1
1
1
1
Go to: www.freescale.com
M1
0
0
1
1
0
0
1
1
MC145574
M0
0
1
0
1
0
1
0
1
DCL = 1.536 MHz, Terminal Mode
GCI TE Master Mode
DCL = 2.048 MHz
DCL = 512 kHz
Reserved
Reserved
Reserved
Reserved
Reserved
6–7