MC145574APBR2 Freescale Semiconductor, MC145574APBR2 Datasheet - Page 89

• Manufacturer Part Number: MC145574APBR2
• Manufacturer: Freescale Semiconductor

Specifications of MC145574APBR2

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
9.16
9.17
Refer to Section 11 for a detailed description of this mode. Application of a hardware or software reset
resets this bit to 0.
BR13(2) — NT: Force Echo Channel to Zero
This bit is a read/write bit and is only applicable to the NT mode of operation. When the MC145574
is configured as an NT and this bit is 0, the device functions normally. When this bit is 1, the NT forces
the transmitted E bits to be 0. This feature is used for test purposes when the NT wishes to communicate
to the TEs on the passive bus that they should disengage from the D channel. Application of either
a hardware or a software reset resets this bit to 0.
BR13(1) —NT: Not Applicable
This bit is a read/write bit and is only applicable to the TE mode of operation. When the MC145574
is configured as a TE and this bit is 0, the device functions normally. When this bit is 1, data is presented
on IDL2 Tx in the special case where the TE is synchronized to INFO 4 incoming from the NT but
its transmitter is not fully active (i.e., not transmitting INFO 3). This feature is useful when the MC145574
is in the transmit power down mode (NR0(2) = 1) and it is desired to continue to process data from
the NT. This bit has no effect when the device is fully active (transmitting INFO 3 and receiving INFO 4).
When BR13(1) = 0 and the device is not fully active, “idle 1s” will be presented on IDL2 Tx. Application
of either a hardware or a software reset resets this bit to 0.
BR13(0)
This bit is reserved.
BR14
Byte register 14 is a read/write register. It is reserved for Motorola use only.
BR15
BR15(7) — Overlay Register Enabled
When the device is initialized, this bit is a logic 0. When set to a logic 0, operation of the MC145574
register map is identical to that of the MC145474. When set to a logic 1, a second set overlay register
is enabled. The overlay register map allows access to the TSA registers required by the IDL2 and
also to a GCI control register.
BR15(5:0) — Device Revision Identification, Rev (5:0)
The Rev (5:0) bits indicate the revision status of the device. These bits are read only and can only
be modified by altering the device mask. Rev (5:0) is set to 11H for G20R1 mask set and to 03H
for F57J4 mask set. See Section 20 for F57J4 mask set differences.
BR14
BR15
Reserved
Register
Enabled
Overlay
TE: Force IDL2 Tx
TE: Not Applicable
(7)
(7)
Freescale Semiconductor, Inc.
For More Information On This Product,
Reserved
(6)
(6)
Go to: www.freescale.com
Reserved
Rev 5
(5)
(5)
MC145574
Reserved
Rev 4
(4)
(4)
Reserved
Rev 3
(3)
(3)
Reserved
Rev 2
(2)
(2)
Reserved
Rev 1
(1)
(1)
Reserved
Rev 0
(0)
(0)
9–13