MC145574APBR2 Freescale Semiconductor, MC145574APBR2 Datasheet - Page 66

• Manufacturer Part Number: MC145574APBR2
• Manufacturer: Freescale Semiconductor

Specifications of MC145574APBR2

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

7–4
7.2.19
7.2.20
7.2.21
7.2.22
7.2.23
7.2.24
7.2.25
7.2.26
In IDL2 mode, this pin can also be used as the 8 kHz frame sync (FST) for the transmit path. In this
mode, the pin is bidirectional, the direction depending on whether the device is an IDL2 master or
slave. FST only operates when dual frame sync mode has been enabled via the SCP.
In GCI mode, this pin can be an output clock (BCL). BCL is a bit rate clock that is half the frequency
of the DCL clock and is synchronous with FSC. This clock can be used as the data clock for standard
devices such as a codec. BCL must be enabled via the GCI Monitor channel.
Loopback active (LBA) is the default function for both the IDL2 and GCI modes. This pin is initially
an output. The LBA pin is normally low but when a loopback is activated within the device, this pin
will transition to a high during the time that the loopback is enabled. This pin can be redefined by
writing to internal registers within the device.
IRQ/IND
This pin is an open drain output that pulls low when the device wants to inform the microprocessor
that a status change has occurred. This pin returns to high impedance after clearing the interrupt condi-
tion via the SCP.
In GCI mode, this pin is GCI_IND. It is an open drain output and is driven low to indicate that GCI
mode is enabled.
V DD 3
This pin is the 3 V regulated supply output used to power the internal digital circuitry. This pin requires
an external smoothing capacitor to be connected to ground (100 nF).
V DD I/O
This is the positive supply pin for the output drivers. This pin should be connected to V DD 5, if 5 V
drivers are required; or the 3 V regulator output, V DD 3, if 3 V drivers are required. For further informa-
tion, refer to the section on Power Supply Strategy.
V DD 5
This is the positive supply pin and is normally 5 V 5%. It should have a capacitor of 100 nF connected
to ground. For further information, refer to the section on Power Supply Strategy.
EXTAL
This pin is an output and should be connected to the 15.36 MHz crystal using the circuit defined in
Section 14.
XTAL
This pin is an output and should be connected to the 15.36 MHz crystal using the circuit defined in
Section 14, or alternatively it can be driven by an external 15.36 MHz clock source.
TxN, TxP
These two pins form a differential output driver that will connect to the S/T–interface via a transformer.
For further information, refer to Section 16.
RESET
This pin is always an input and is the reset pin for the device. It is active low. When this pin is held
low, a hardware reset is applied and the device is held in the deactivated state. At the initial application
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MC145574
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