PIC18F6585-I/PT Microchip Technology Inc., PIC18F6585-I/PT Datasheet - Page 300
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PIC18F6585-I/PT
Manufacturer Part Number
PIC18F6585-I/PT
Description
64 PIN, 48 KB FLASH, 3328 RAM, 52 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F6585-IPT.pdf
(496 pages)
Specifications of PIC18F6585-I/PT
A/d Inputs
12-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
1024 Bytes
Input Output
53
Interface
CAN/I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
64-pin TQFP
Programmable Memory
48K Bytes
Ram Size
3.3K Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Company:
Part Number:
PIC18F6585-I/PT
Manufacturer:
Microchip Technology
Quantity:
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Part Number:
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Manufacturer:
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PIC18F6585/8585/6680/8680
REGISTER 23-23: BnCON: TX/RX BUFFER n CONTROL REGISTERS IN TRANSMIT MODE
DS30491C-page 298
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
[0
bit 7
Legend:
R = Readable bit
- n = Value at POR
TXBIF: Transmit Buffer Interrupt Flag bit
1 = A message is successfully transmitted
0 = No message was transmitted
TXABT: Transmission Aborted Status bit
1 = Message was aborted
0 = Message was not aborted
TXLARB: Transmission Lost Arbitration Status bit
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
TXERR: Transmission Error Detected Status bit
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
TXREQ: Transmit Request Status bit
1 = Requests sending a message; clears the TXABT, TXLARB, and TXERR bits
0 = Automatically cleared when the message is successfully sent
RTREN: Automatic Remote Transmission Request Enable bit
1 = When a remote transmission request is received, TXREQ will be automatically set
0 = When a remote transmission request is received, TXREQ will be unaffected
TXPRI1:TXPRI0: Transmit Priority bits
11 = Priority Level 3 (highest priority)
10 = Priority Level 2
01 = Priority Level 1
00 = Priority Level 0 (lowest priority)
R/W-0
TXBIF
Note:
Note 1: These registers are available in Mode 1 and 2 only.
n
2: This bit is automatically cleared when TXREQ is set.
3: While TXREQ is set or transmission is in progress, transmit buffer registers remain
4: These bits set the order in which the transmit buffer will be transferred. They do not
5, TXnEN (BSEL0<n>) = 1]
Clearing this bit in software while the bit is set will request a message abort.
read-only.
alter the CAN message identifier.
TXABT
R-0
TXLARB
W = Writable bit
‘1’ = Bit is set
R-0
(3)
TXERR
(4)
R-0
(1)
(1)
(1)
(2)
TXREQ
R/W-0
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
RTREN
R/W-0
2004 Microchip Technology Inc.
x = Bit is unknown
TXPRI1
R/W-0
TXPRI0
R/W-0
bit 0
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