PIC18F6585-I/PT Microchip Technology Inc., PIC18F6585-I/PT Datasheet - Page 35

• Manufacturer Part Number: PIC18F6585-I/PT
• Description: 64 PIN, 48 KB FLASH, 3328 RAM, 52 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F6585-I/PT

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 53
• Interface: CAN/I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 64-pin TQFP
• Programmable Memory: 48K Bytes
• Ram Size: 3.3K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

3.0
The PIC18F6585/8585/6680/8680 devices differentiate
between various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” on Power-on Reset, MCLR, WDT Reset, Brown-
out Reset, MCLR Reset during Sleep and by the
RESET instruction.
FIGURE 3-1:
 2004 Microchip Technology Inc.
MCLR
OSC1
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
V
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
Watchdog Timer (WDT) Reset (during normal
operation)
Programmable Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
DD
Instruction
RESET
RESET
2: See Table 3-1 for time-out situations.
Pointer
Stack
RC OSC
OST/PWRT
On-chip
Brown-out
V
Module
Detect
DD
WDT
Reset
(1)
Rise
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Stack Full/Underflow Reset
OST
PWRT
External Reset
10-bit Ripple Counter
Time-out
Reset
10-bit Ripple Counter
WDT
BOREN
Power-on Reset
SLEEP
PIC18F6585/8585/6680/8680
Enable PWRT
Enable OST
Most registers are not affected by a WDT wake-up
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
POR and BOR, are set or cleared differently in different
Reset situations, as indicated in Table 3-2. These bits
are used in software to determine the nature of the
Reset. See Table 3-3 for a full description of the Reset
states of all registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.
The Enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses. The MCLR pin is not driven low by
any internal Resets, including the WDT.
(2)
S
R
DS30491C-page 33
Q
Chip_Reset