PIC16C72A-04/SO Microchip Technology Inc., PIC16C72A-04/SO Datasheet - Page 44
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PIC16C72A-04/SO
Manufacturer Part Number
PIC16C72A-04/SO
Description
28 PIN, 3.5 KB OTP, 128 RAM, 22 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16C72A-04SO.pdf
(120 pages)
Specifications of PIC16C72A-04/SO
A/d Inputs
5-Channel, 8-Bit
Cpu Speed
5 MIPS
Eeprom Memory
0 Bytes
Input Output
22
Memory Type
OTP
Number Of Bits
8
Package Type
28-pin SOIC
Programmable Memory
3.5K Bytes
Ram Size
128 Bytes
Speed
4 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2.5-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC16C62B/72A
8.3.1.3
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and the CKP will be cleared by
hardware, holding SCL low. Slave devices cause the
master to wait by holding the SCL line low. The transmit
data is loaded into the SSPBUF register, which in turn
loads the SSPSR register. When bit CKP (SSP-
CON<4>) is set, pin RC3/SCK/SCL releases SCL.
When the SCL line goes high, the master may resume
operating the SCL line and receiving data. The master
must monitor the SCL pin prior to asserting another
clock pulse. The slave devices may be holding off the
master by stretching the clock. The eight data bits are
FIGURE 8-4:
DS35008B-page 44
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
S
TRANSMISSION
A7
1
Data in
sampled
I
2
C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
A6
2
A5
Receiving Address
3
A4
4
A3
5
A2
6
A1
7
R/W = 1
8
Preliminary
9
ACK
responds to SSPIF
while CPU
SCL held low
shifted out on the falling edge of the SCL input. This
ensures that the SDA signal is valid during the SCL
high time (Figure 8-4).
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register used to determine the status of
the byte. Flag bit SSPIF is set on the falling edge of the
ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master-
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then the
data transfer is complete. When the ACK is latched by
the slave, the slave logic is reset (resets SSPSTAT reg-
ister) and the slave then monitors for another occur-
rence of the START bit. If the SDA line was low (ACK),
the transmit data must be loaded into the SSPBUF reg-
ister, which also loads the SSPSR register. Then pin
RC3/SCK/SCL should be enabled by setting bit CKP.
D7
1
SSPBUF is written in software
D6
2
cleared in software
Set bit after writing to SSPBUF
(the SSPBUF must be written-to
before the CKP bit can be set)
D5
3
D4
4
Transmitting Data
D3
5
1999 Microchip Technology Inc.
D2
6
From SSP interrupt
service routine
D1
7
D0
8
ACK
9
P