PIC16C72A-04/SO Microchip Technology Inc., PIC16C72A-04/SO Datasheet - Page 46
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PIC16C72A-04/SO
Manufacturer Part Number
PIC16C72A-04/SO
Description
28 PIN, 3.5 KB OTP, 128 RAM, 22 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16C72A-04SO.pdf
(120 pages)
Specifications of PIC16C72A-04/SO
A/d Inputs
5-Channel, 8-Bit
Cpu Speed
5 MIPS
Eeprom Memory
0 Bytes
Input Output
22
Memory Type
OTP
Number Of Bits
8
Package Type
28-pin SOIC
Programmable Memory
3.5K Bytes
Ram Size
128 Bytes
Speed
4 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2.5-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC16C62B/72A
REGISTER 8-1:
DS35008B-page 46
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
R/W-0 R/W-0
SMP
SMP: SPI data input sample phase
SPI Master Operation
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
I
This bit must be maintained clear
CKE: SPI Clock Edge Select
SPI Mode
CKP = 0
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
I
This bit must be maintained clear
D/A: Data/Address bit (I
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit (I
detected last, SSPEN is cleared)
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
S: Start bit (I
detected last, SSPEN is cleared)
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
R/W: Read/Write bit information (I
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next start bit, stop bit, or ACK bit.
1 = Read
0 = Write
UA: Update Address (10-bit I
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
CKE
2
2
C Mode
C Mode
SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R-0
D/A
2
C mode only)
2
2
C mode only. This bit is cleared when the SSP module is disabled, or when the Start bit is
C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit is
2
R-0
C modes)
P
2
C mode only)
2
C mode only)
R-0
S
2
C mode only)
Preliminary
R/W
R-0
R-0
UA
R-0
BF
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read
- n =Value at POR reset
1999 Microchip Technology Inc.
as ‘0’