PIC16C72A-04/SO Microchip Technology Inc., PIC16C72A-04/SO Datasheet - Page 52
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PIC16C72A-04/SO
Manufacturer Part Number
PIC16C72A-04/SO
Description
28 PIN, 3.5 KB OTP, 128 RAM, 22 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16C72A-04SO.pdf
(120 pages)
Specifications of PIC16C72A-04/SO
A/d Inputs
5-Channel, 8-Bit
Cpu Speed
5 MIPS
Eeprom Memory
0 Bytes
Input Output
22
Memory Type
OTP
Number Of Bits
8
Package Type
28-pin SOIC
Programmable Memory
3.5K Bytes
Ram Size
128 Bytes
Speed
4 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2.5-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC16C62B/72A
9.1
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (C
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 9-2. The source
impedance (R
impedance directly affect the time required to charge
the capacitor C
impedance varies over the device voltage (V
source impedance affects the offset voltage at the ana-
log input (due to pin leakage current). The maximum
recommended impedance for analog sources is 10
k . After the analog input channel is selected
(changed), this acquisition must pass before the con-
version can be started.
FIGURE 9-2:
EQUATION 9-1:
DS35008B-page 52
T
ACQ
A/D Acquisition Requirements
=
=
S
Amplifier Settling Time +
Hold Capacitor Charging Time +
Temperature Coefficient
T
T
T
T
) and the internal sampling switch (R
AMP
AMP
C
COFF
HOLD
= - (51.2pF)(1k + R
ANALOG INPUT MODEL
Legend C
+ T
= 5 S
= (Temp -25 C)(0.05 S/ C)
VA
. The sampling switch (R
ACQUISITION TIME
C
Rs
+ T
V
I leakage
R
SS
C
T
PIN
IC
HOLD
COFF
ANx
C
5 pF
HOLD
PIN
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
) must be allowed
SS
+ R
S
) In(1/511)
V
DD
DD
). The
V
V
T
T
Preliminary
SS
SS
= 0.6V
= 0.6V
)
)
I leakage
± 500 nA
To calculate the minimum acquisition time, T
Equation 9-1. This equation calculates the acquisition
time to within 1/2 LSb error (512 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified accuracy.
In general;
Assuming R
T
By increasing V
can be substantially reduced.
R
ACQ
Note:
IC
1k
13.0 Sec
V
SS R
DD
Sampling
Switch
When the conversion is started, the hold-
ing capacitor is disconnected from the
input pin.
Vdd
Temp. = 50 C (122 F)
S
6V
5V
4V
3V
2V
SS
DD
= 10k
= 3.0V (R
and reducing R
5 6 7 8 9 10 11
V
SS
C
= DAC capacitance
= 51.2 pF
R
(k )
HOLD
SS
1999 Microchip Technology Inc.
SS
= 10k
S
and Temp., T
ACQ
, see
ACQ