ADC10065CIMT/HALF National Semiconductor, ADC10065CIMT/HALF Datasheet - Page 18

• Manufacturer Part Number: ADC10065CIMT/HALF
• Manufacturer: National Semiconductor

Specifications of ADC10065CIMT/HALF

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1.8 OUTPUT PINS
The ADC10065 has 10 TTL/CMOS compatible Data Output
pins. The offset binary data is present at these outputs while
the DF and STBY pins are low. Be very careful when driving
a high capacitance bus. The more capacitance the output
drivers must charge for each conversion, the more instanta-
neous digital current flows through V
large charging current spikes can cause on-chip noise and
couple into the analog circuitry, degrading dynamic perfor-
mance. Adequate bypassing, limiting output capacitance and
careful attention to the ground plane will reduce this problem.
Additionally,
IRS Pin
Floating
V
V
DDA
SSA
bus
TABLE 1. IRS Pin Functions
capacitance
FIGURE 5. A Simple Application Using a Differential Driving Source
Full-Scale Input
beyond
2.0V
1.5V
1.0V
DDIO
P-P
P-P
P-P
and V
the
SSIO
specified
. These
18
10 pF/pin will cause t
erly latch the ADC output data. The result could be an appar-
ent reduction in dynamic performance. To minimize noise due
to output switching, minimize the load currents at the digital
outputs. This can be done by minimizing load capacitance
and by connecting buffers between the ADC outputs and any
other circuitry, which will isolate the outputs from trace and
other circuit capacitances and limit the output currents, which
could otherwise result in performance degradation. Only one
driven input should be connected to the ADC output pins.
While the t
a simple way to capture a valid output is to latch the data on
the rising edge of the conversion clock.
1.9 APPLICATION SCHEMATICS
The following figures show simple examples of using the
ADC10065. Figure 5 shows a typical differentially driven in-
put. Figure 6 shows a single ended application circuit.
OD
time provides information about output timing,
OD
to increase, making it difficult to prop-
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