ADC10065CIMT/HALF National Semiconductor, ADC10065CIMT/HALF Datasheet - Page 7

• Manufacturer Part Number: ADC10065CIMT/HALF
• Manufacturer: National Semiconductor

Specifications of ADC10065CIMT/HALF

• Lead Free Status / Rohs Status: Supplier Unconfirmed

CLK, DF, STBY, SENSE
f
f
t
t
t
t
t
t
Symbol
CLK
CLK
CH
CL
OD
AD
AJ
STBY
AC Electrical Characteristics
Unless otherwise specified, the following specifications apply for V
STBY = 0V, V
T
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = V
Note 3: When the voltage at any pin exceeds the power supplies (V
package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
pin TSSOP, θ
of this device under normal operation will typically be about 68.6 mW. The values for maximum power dissipation listed above will be reached only when the
ADC10065 is operated in a severe fault condition.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.
Note 6: The 235°C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR) the following conditions apply: Maintain the temperature at the
top of the package body above 183°C for a minimum of 60 seconds. The temperature measured on the package body must not exceed 220°C. Only one excursion
above 183°C is allowed per reflow cycle.
Note 7: The analog inputs are protected as shown below. Input voltage magnitude up to 500 mV beyond the supply rails will not damage this device. However,
input errors will be generated if the input goes above V
Note 8: VCOM is a typical value, measured at room temperature. It is not guaranteed by test. Do not load this pin.
Note 9: To guarantee accuracy, it is required that |V
Note 10: With the test condition for 2 V
Note 11: Typical figures are at T
Quality Level).
Note 12: Timing specifications are tested at TTL logic levels, V
Note 13: Optimum dynamic performance will be obtained by keeping the reference input in the +1.2V.
Note 14: I
voltage, V
output driver supply voltage, C
Note 15: Power consumption includes output driver power. (f
Note 16: The input bandwidth is limited using a capacitor between V
MAX
1
2
: all other limits T
Maximum Clock Frequency
Minimum Clock Frequency
Clock High Time
Clock Low Time
Conversion Latency
Data Output Delay after a Rising Clock
Edge
Aperture Delay
Aperture Jitter
Over Range Recovery Time
Standby Mode Exit Cycle
DDIO
DR
, and the rate at which the outputs are switching (which is signal dependent). I
JA
is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply
is 96°C/W, so P
REF
= 1.20V (External), f
A
Parameter
= 25°C
n
D
is the total load capacitance on the output pin, and f
A
MAX = 1,302 mW at 25°C and 677 mW at the maximum operating ambient temperature of 85°C. Note that the power dissipation
= T
J
P-P
= 25°C and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing
JA
differential input, the 10-bit LSB is 1.95 mV.
), and the ambient temperature (T
CLK
= 65 MHz, 50% Duty Cycle, C
DDA
DDA
–V
J
max) for this device is 150°C. The maximum allowable power dissipation is dictated by T
DDIO
or V
SSA
T = 25°C
Differential V
±3V to 0V to get accurate
conversion
IN
|
DDIO
IL
= V
= 0 MHz).
≤
= 0.4V for a falling edge, and V
IN
100 mV and separate bypass capacitors are used at each power supply pin.
SSIO
and below V
< V
IN
−
Conditions
= 0V, unless otherwise specified.
SSA
and V
or V
IN
A
), and can be calculated using the formula P
IN
7
IN
step from
+
SSA
.
> V
SSA
n
or V
DDA
is the average frequency at which the pin is toggling.
= V
), the current at that pin should be limited to 25 mA. The 50 mA maximum
SSIO
L
DR
= 10 pF/pin. Boldface limits apply for T
SSIO
.
20077907
= V
IH
= 0V, V
DR
= 2.4V for a rising edge.
(Note 12)
x (C
Min
0
2
1
x f
DDA
0
+ C
= +3.0V, V
1
x f
(Note 12)
1
+ C
7.69
7.69
Typ
3.4
20
20
1
2
1
D
2
MAX = (T
+ f
DDIO
2
+....C
= +2.5V, V
(Note 12)
J
11
max − T
Max
65
x f
6
5
6
11
) where V
A
A
)/θ
IN
= T
www.national.com
J
JA
Clock Cycle
max, the
= 2 V
MHz (min)
ps (RMS)
. In the 28-
MIN
Cycles
Cycles
DR
Units
MHz
ns
ns
ns
ns
ns
is the
to
P-P
,