LAN8187I-JT SMSC, LAN8187I-JT Datasheet - Page 45

• Manufacturer Part Number: LAN8187I-JT
• Description: TXRX ETHERNET 10/100 ESD PROT
• Manufacturer: SMSC
• Type: Transceiverr

Specifications of LAN8187I-JT

• Protocol: Ethernet
• Voltage - Supply: 1.6 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: Q4223799

High-Performance MII and RMII 10/100 Ethernet PHY with HP Auto-MDIX
Datasheet
SMSC LAN8187/LAN8187I
ADDRESS
ADDRESS
18.15:14
17.7:5
18.13
18.12
18.10
18.11
18.9
18.8
17.9
17.8
17.4
17.3
17.2
17.1
17.0
Good Link Status
FARLOOPBACK
CLKSELFREQ
ENERGYON
REFCLKEN
PHYADBP
MIIMODE
FASTEST
Reserved
Reserved
Reserved
DSPBP
ADCBP
PLLBP
NAME
SQBP
NAME
Force
Table 5.38 Register 17 - Mode Control/Status (continued)
Table 5.39 Register 18 - Special Modes
MII Mode : set the mode of the MII:
0 – MII interface.
1 – RMII interface
Clock In Selected Frequency. Set the requested input
clock frequency. This bit drives signal that goes to
external logic of the Phy and select the desired
frequency of the input clock:
0 – the clock frequency is 25MHz
1 – Reserved
DSP Bypass mode. Used only in special lab tests.
SQUELCH Bypass mode.
PLL Bypass mode.
ADC Bypass mode.
Force the module to the FAR Loop Back mode, i.e. all
the received packets are sent back simultaneously (in
100Base-TX only). This bit is only active in RMII
mode. In this mode the user needs to supply a 50MHz
clock to the PHY. This mode works even if MII Isolate
(0.10) is set.
Auto-Negotiation Test Mode
0 = normal operation
1 = activates test mode
Write as 0, ignore on read.
1= Enables special filtering using a 50 MHz Clock in
10Base-T mode.
1 = PHY disregards PHY address in SMI access
0 = normal operation;
1 = force 100TX- link active;
Note:
ENERGYON – indicates whether energy is detected
on the line (see
Power-Down," on page
energy is detected within 256ms. Reset to “1” by
hardware reset, unaffected by SW reset.
Write as “0”. Ignore on read.
write.
This bit should be set only during lab testing
DATASHEET
Section 5.4.5.2, "Energy Detect
DESCRIPTION
DESCRIPTION
45
50); it goes to “0” if no valid
MODE
MODE
NASR
NASR
NASR
NASR
NASR
NASR
NASR
RW,
RW,
RW,
Revision 0.6 (02-24-06)
RW
RW
RW
RW
RW
RW
RW,
RO,
RW,
RW,
RO
DEFAULT
DEFAULT
0
0
0
0
0
1
0
0
0