MM912H634CM1AER2 Freescale Semiconductor, MM912H634CM1AER2 Datasheet - Page 194

• Manufacturer Part Number: MM912H634CM1AER2
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CM1AER2

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Providing a small overhead on the pulse length in order to assure the SYNC pulse will not be misinterpreted by the target. See
Section 4.31.4.9, “SYNC — Request Timed Reference
Figure 63
the command is aborted a new command could be issued by the host computer.
Figure 64
connected to the target BKGD pin and the target is already in debug active mode. Consider that the target CPU is executing a
pending BDM command at the exact moment the POD is being connected to the BKGD pin. In this case, an ACK pulse is issued
along with the SYNC command. In this case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse.
Since this is not a probable situation, the protocol does not prevent this conflict from happening.
The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE BDM commands. This
provides backwards compatibility with the existing POD devices which are not able to execute the hardware handshake protocol.
It also allows for new POD devices, that support the hardware handshake protocol, to freely communicate with the target device.
If desired, without the need for waiting for the ACK pulse.
The commands are described as follows:
Freescale Semiconductor
(Target MCU)
Drives SYNC
To BKGD Pin
BKGD Pin
Target MCU
BDM Clock
BKGD Pin
BKGD Pin
Drives to
shows a SYNC command being issued after a READ_BYTE, which aborts the READ_BYTE command. Note that, after
shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could occur if a POD device is
Host
READ_BYTE
Figure 63
This information is being provided so that the MCU integrator will be aware that such a
conflict could occur.
the READ_BYTE Command
READ_BYTE CMD is Aborted
Host
does not represent the signals in a true timing scale
and Starts to Execute
by the SYNC Request
Figure 63. ACK Abort Procedure at the Command Level
Memory Address
Target
Host SYNC Request Pulse
Figure 64. ACK Pulse and SYNC Request Conflict
BDM Decode
(Out of Scale)
ACK Pulse
16 Cycles
MM912_634 Advance Information, Rev. 4.0
Host and
Target Drive
to BKGD Pin
At Least 128 Cycles
Pulse”.
NOTE
NOTE
Electrical Conflict
High-Impedance
READ_STATUS
Host
SYNC Response
From the Target
(Out of Scale)
Target
New BDM Command
New BDM Command
Host
Speedup Pulse
Target
194