MM912H634CM1AER2 Freescale Semiconductor, MM912H634CM1AER2 Datasheet - Page 265

• Manufacturer Part Number: MM912H634CM1AER2
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CM1AER2

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.38.4
4.38.4.1
The PLL is used to generate a high speed PLLCLK based on a low frequency REFCLK.
The REFCLK is by default the IRCCLK which is trimmed to f
If using the oscillator (OSCE=1) REFCLK will be based on OSCCLK. For increased flexibility, OSCCLK can be divided in a range
of 1 to 16 to generate the reference frequency REFCLK using the REFDIV[3:0] bits. Based on the SYNDIV[5:0] bits the PLL
generates the VCOCLK by multiplying the reference clock by a 2, 4, 6,... 126, 128. Based on the POSTDIV[4:0] bits the VCOCLK
can be divided in a range of 1,2, 3, 4, 5, 6,... to 32 to generate the PLLCLK.
Freescale Semiconductor
RCEXA
LVRXS
LVRFS
If Oscillator is enabled (OSCE=1)
If Oscillator is disabled (OSCE=0)
f VCO
If PLL is locked (LOCK=1)
If PLL is not locked (LOCK=0)
If PLL is selected (PLLSEL=1)
LVRS
Field
5
4
3
0
=
Functional Description
2
Low Voltage Reset Detect VDD Status Bit — This read-only status bit reflects the Status of the Low Voltage Reset on VDD
when core reset disabled for parametric tests. Writes have no effect.
0 Input voltage V
1 Input voltage V
Low Voltage Reset Detect VDDF Status Bit — This read-only status bit reflects the Status of the Low Voltage Reset on VDDF
when core reset disabled for parametric tests. Writes have no effect.
0 Input voltage V
1 Input voltage V
Low Voltage Reset Detect VDDX Status Bit — This read-only status bit reflects the Status of the Low Voltage Reset on VDDX
when core reset disabled for parametric tests. Writes have no effect.
0 Input voltage V
1 Input voltage V
Autonomous Periodical Interrupt clock (ACLK) External Access Enable Bit — The Autonomous Periodical Interrupt clock
(ACLK) can be mapped also to an output pin. See Section 1 (Device Overview) and Section Port Integration Module for details.
0 The Autonomous Periodical Interrupt clock (ACLK) is not mapped to an output pin.
1 The Autonomous Periodical Interrupt clock (ACLK) is mapped to an output pin if APIFE is set and APIEA=0.
Phase-locked Loop with Internal Filter (PLL)

f REF


SYNDIV
DD
DD
DDF
DDF
DDX
DDX
is above level V
is below level V
is above level V
is below level V
+
is above level V
is below level V
1
Table 381. CPMUTEST2 Field Descriptions
f bus
f PLL
f PLL

MM912_634 Advance Information, Rev. 4.0
=
=
=
f REF
f REF
f PLL
------------
--------------------------------------- -

f VCO
------------- -
POSTDIV
2
LVRA
LVRA
4
LVRFA
LVRXA
LVRFA
LVRXA
=
=
f VCO
and device is in Full Performance Mode (FPM).
or device is in Reduced Performance Mode (RPM).
------------------------------------ -

f IRC 1 M
REFDIV
and device is in FPM.
or device is in RPM.
and device is in FPM.
or device is in RPM.
IRC1M_TRIM
f OSC
+
1
Description

+
1
=1.0 MHz.

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