PIC24EP64MC204-E/PT Microchip Technology, PIC24EP64MC204-E/PT Datasheet - Page 125

• Manufacturer Part Number: PIC24EP64MC204-E/PT
• Description: 16 Bit MCU, 64KB Flash, 8KB RAM, 60 MHz, 44 Pin, MCPWM,QEI, 3 OpAmp, 4 Comp, PTG
• Manufacturer: Microchip Technology

7.0
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X, and PIC24EPXXXGP/MC20X interrupt controller
reduces the numerous peripheral interrupt request sig-
nals to a single interrupt request signal to the
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X,
and PIC24EPXXXGP/MC20X CPU.
The interrupt controller has the following features:
• Up to eight processor exceptions and software
• Eight user-selectable priority levels
• Interrupt Vector Table (IVT) with a unique vector
• Fixed priority within a specified user priority level
• Fixed interrupt entry and return latencies
 2011-2012 Microchip Technology Inc.
traps
for each interrupt or exception source
Note 1: This data sheet summarizes the features
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
2: Some registers and associated bits
INTERRUPT CONTROLLER
of
dsPIC33EPXXXMC20X/50X,
PIC24EPXXXGP/MC20X
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer
(DS70600) of the “dsPIC33E/PIC24E
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
to
the
Section
dsPIC33EPXXXGP50X,
6.
“Interrupts”
families
and
of
in
7.1
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X, and PIC24EPXXXGP/MC20X Interrupt Vector
Table (IVT), shown in
memory, starting at location 000004h. The IVT contains
seven non-maskable trap vectors and up to 114
sources of interrupt. In general, each interrupt source
has its own vector. Each interrupt vector contains a 24-
bit-wide address. The value programmed into each
interrupt vector location is the starting address of the
associated Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to their position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with vector 0 takes priority over interrupts at any other
vector address.
7.2
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X, and PIC24EPXXXGP/MC20X devices clear their
registers in response to a Reset, which forces the PC
to zero. The device then begins program execution at
location 0x000000. A GOTO instruction at the Reset
address can redirect program execution to the
appropriate start-up routine.
Note:
Interrupt Vector Table
Reset Sequence
Any unimplemented or unused vector
locations
programmed with the address of a default
interrupt handler routine that contains a
RESET instruction.
Figure
in
the
7-1, resides in program
IVT
DS70657F-page 125
should
be