PIC24EP64MC204-E/PT Microchip Technology, PIC24EP64MC204-E/PT Datasheet - Page 283

• Manufacturer Part Number: PIC24EP64MC204-E/PT
• Description: 16 Bit MCU, 64KB Flash, 8KB RAM, 60 MHz, 44 Pin, MCPWM,QEI, 3 OpAmp, 4 Comp, PTG
• Manufacturer: Microchip Technology

20.3
REGISTER 20-1:
 2011-2012 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6
Note 1:
UARTEN
R/W-0 HC
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
WAKE
R/W-0
2:
3:
4:
(1)
Refer to Section 17. “UART” (DS70582) in the “dsPIC33E/PIC24E Family Reference Manual” for infor-
mation on enabling the UART module for receive or transmit operation.
This feature is only available for the 16x BRG mode (BRGH = 0).
This feature is only available on 44-pin and 64-pin devices.
This feature is only available on 64-pin devices.
UART Control Registers
UARTEN: UARTx Enable bit
1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0 = UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption
Unimplemented: Read as ‘0’
USIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
IREN: IrDA
1 = IrDA encoder and decoder enabled
0 = IrDA encoder and decoder disabled
RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin in Simplex mode
0 = UxRTS pin in Flow Control mode
Unimplemented: Read as ‘0’
UEN<1:0>: UARTx Pin Enable bits
11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin controlled by PORT latches
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by PORT latches
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins controlled by
WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit
1 = UARTx continues to sample the UxRX pin; interrupt generated on falling edge; bit cleared
0 = No wake-up enabled
LPBACK: UARTx Loopback Mode Select bit
1 = Enable Loopback mode
0 = Loopback mode is disabled
LPBACK
R/W-0
minimal
in hardware on following rising edge
U-0
—
PORT latches
UxMODE: UART
®
Encoder and Decoder Enable bit
W = Writable bit
HC = Hardware cleared
‘1’ = Bit is set
R/W-0 HC
ABAUD
USIDL
R/W-0
x
MODE REGISTER
URXINV
IREN
R/W-0
R/W-0
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
RTSMD
(2)
R/W-0
R/W-0
BRGH
R/W-0
U-0
—
PDSEL<1:0>
(4)
x = Bit is unknown
R/W-0
R/W-0
UEN<1:0>
DS70657F-page 283
STSEL
R/W-0
R/W-0
bit 8
bit 0
(3)
(4)