PIC32MX675F512L-80V/BG Microchip Technology, PIC32MX675F512L-80V/BG Datasheet - Page 82
![512 KB Flash, 64 KB RAM, USB-OTG, Ethernet, 80 MHz, 10-Bit ADC, DMA 121 XBGA 10x](/photos/40/62/406286/landingpagemicrochippic32_sml.jpg)
PIC32MX675F512L-80V/BG
Manufacturer Part Number
PIC32MX675F512L-80V/BG
Description
512 KB Flash, 64 KB RAM, USB-OTG, Ethernet, 80 MHz, 10-Bit ADC, DMA 121 XBGA 10x
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.PIC32MX575F256H-80VPT.pdf
(256 pages)
Specifications of PIC32MX675F512L-80V/BG
Processor Series
PIC32MX6xx
Core
MIPS
Data Bus Width
32 bit
Program Memory Type
Flash
Program Memory Size
512 KB
Data Ram Size
64 KB
Interface Type
USB, I2C, UART, RS-232, RS-485, SPI
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
5
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
XBGA-100
Operating Temperature Range
- 40 C to + 85 C
Supply Current (max)
10 mA
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
-
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX675F512L-80V/BG
Manufacturer:
Microchip Technology
Quantity:
10 000
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TABLE 4-13:
Legend:
Note
6630
6640
6800 U2MODE
6810
6820
6830
6840
6A00 U5MODE
6A10
6A20
6A30 U5RXREG
6A40
1:
U6RXREG
U2RXREG
U2TXREG
U5TXREG
U6BRG
U2BRG
U5BRG
U2STA
U5STA
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See
(1)
(1)
(1)
(1)
(1)
(1)
(1)
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
UART1 THROUGH UART6 REGISTER MAP (CONTINUED)
31/15
ON
ON
UTXISEL<1:0>
UTXISEL<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30/14
FRZ
FRZ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXINV
UTXINV
29/13
SIDL
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
URXEN
URXEN
28/12
IREN
IREN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXBRK
UTXBRK
RTSMD
27/11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXEN
UTXEN
26/10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXBF
UTXBF
25/9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UEN<1:0>
ADM_EN
ADM_EN
TRMT
TRMT
24/8
RX8
TX8
RX8
TX8
RX8
—
—
—
—
—
—
—
—
—
—
—
BRG<15:0>
BRG<15:0>
BRG<15:0>
Bits
WAKE
WAKE
23/7
URXISEL<1:0>
URXISEL<1:0>
—
—
—
—
—
—
—
—
—
—
LPBACK
LPBACK
22/6
—
—
—
—
—
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
ABAUD
ADDEN
ABAUD
ADDEN
21/5
—
—
—
—
—
—
—
—
—
—
RXINV
RIDLE
RXINV
RIDLE
Transmit Register
Transmit Register
Receive Register
Receive Register
Receive Register
20/4
—
—
—
—
—
—
—
—
—
—
ADDR<7:0>
ADDR<7:0>
BRGH
BRGH
PERR
PERR
19/3
—
—
—
—
—
—
—
—
—
—
FERR
FERR
18/2
—
—
—
—
—
—
—
—
—
—
PDSEL<1:0>
PDSEL<1:0>
for more information.
OERR
OERR
17/1
—
—
—
—
—
—
—
—
—
—
URXDA
URXDA
STSEL
STSEL
16/0
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0110
0000
0000
0000
0000
0000
0000
0000
0000
0000
0110
0000
0000
0000
0000
0000
0000
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