ZL2106ALCFTK Intersil, ZL2106ALCFTK Datasheet - Page 21

• Manufacturer Part Number: ZL2106ALCFTK
• Description: 6A Digital DC-DC Converter W/ DDC - TR1K
• Manufacturer: Intersil
• Series: -r
• Type: Step-Down (Buck), PWM - Voltage Moder

Specifications of ZL2106ALCFTK

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.54 V ~ 5.5 V
• Current - Output: 6A
• Frequency - Switching: 200kHz ~ 1MHz
• Voltage - Input: 4.5 V ~ 14 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

for more information on configuring tracking mode using PMBus
commands.
Figure 23 is an example of a basic pin-strap tracking
configuration. The VTRK pin is an analog input that, when
tracking mode is enabled, the voltage applied to the VTRK pin
performs as a reference for the device's output voltage. The
ZL2106 offers two modes of tracking: coincident and ratiometric.
Figures 20 and 21 illustrate the output voltage waveform for the
two tracking modes.
1. Coincident. This mode configures the ZL2106 to ramp its
a. Track at 100% V
b. Track at 100% VTRK limited. Member rail tracks the
2. Ratiometric. This mode configures the ZL2106 to ramp its
a. Track at 50% V
b. Track at 50% VTRK limited. Member rail tracks the reference
A.
B.
0
0
SDA
SCL
Track @ 100% Vtrk Limited
Vref = Vmem
Track @ 100% Vout Limited
Vref > Vmem
output voltage at the same rate as the voltage applied to the
VTRK pin. Two options are available for this mode;
reference at the instantaneous voltage value applied to the
VTRK pin, Figure 20 (B).
output voltage as a percentage of the voltage applied to the
VTRK pin. The default setting is 50%, but an external resistor
may be used to configure a different tracking ratio.
rail and stops when the member reaches 50% of the target
voltage, Figure 21 (A).
at the instantaneous voltage value applied to the VTRK pin
until the member rail reaches 50% of the reference rail
voltage, or if the member is configured to less than 50% of the
reference the member will achieve its configured target,
Figure 21 (B).
EN
EN
rail and stops when the member reaches its target voltage,
Figure 20 (A).
FIGURE 19. BASIC I
To n Dly
REFERENCE
Ton Dly
SDA
ZL2106
FIGURE 20. COINCIDENT TRACKING
VRef
VRef
SCL
OUT
OUT
SW
limited. Member rail tracks the reference
limited. Member rail tracks the reference
Coincident Tracking
L4
2
VOUT_R
C TRACKING CONFIGURATION
21
Toff Dly
VTRK
Toff Dly
SDA SCL
MEMBER
ZL2106
SW
Vmem
Vmem
L3
VOUT_M
Vref=1.8V
Vmem=0.9V
Vref=1.8V
Vmem=1.8V
ZL2106
Tracking Overview
When the ZL2106 is configured to the voltage tracking mode, the
voltage applied to the VTRK pin acts as a reference for the
member device(s) output regulation. The soft-start values
(Rise/Fall times) are used to calculate the loop gain used during
the turn-on/turn-off ramps, therefore the minimum rise/fall time
has been constrained to 5ms to ensure accuracy. Tracking
accuracy can be improved by increasing the rise and fall times
beyond 5ms.
Tracking Groups
In a tracking group, the device configured to the highest voltage
within the group is defined as the reference device. The device(s)
that track the reference are called the member device(s). The
reference device will control the ramp delay and ramp rate of all
tracking devices and is not placed in the tracking mode.
The reference device is configured to the highest output voltage
for the group and all other device(s) output voltages are meant to
track and never exceed the reference device output voltage.
The reference device must be configured to have a minimum
Time-On Delay and Time-On Rise as shown in Equation 13.
This delay allows the member device(s) to prepare their control
loops for tracking following the assertion of ENABLE.
The member device Time-Off Delay has been redefined to
describe the time that the VTRK pin will follow the reference
voltage after enable is de-asserted. The delay setting sets the
timeout for the member's output voltage to turnoff in the event
that the reference output voltage does not achieve zero volts.
The member device(s) must have a minimum Time-Off Delay of
as shown in Equation 14.
tOFF
It is assumed for a tracking group, that all of the ENABLE pins are
connected together and driven by a single logic source or PMBus
Broadcast Enable is used.
The configuration settings for Figures 20 and 21 are shown
below in Figure 22. In each case the reference and member rise
times are set to the same value.
tON
A.
B.
0
0
DLY(REF)
Track @ 50% Vtrk Limited
Vref = 1.8V
Vmem = 0.8V
Track @ 50% Vout Lim ited
Vref = 1.8V
Vmem = 0.9V
EN
EN
DLY(MEM)
≥ tON
Ton Dly
Ton Dly
≥ tOFF
FIGURE 21. RATIOMETRIC TRACKING
DLY(MEM)
VRef
Vref
DLY(REF)
+ tON
Ratiometric Tracking
+ tOFF
RISE(REF)
FALL(REF)
+ 5ms ≥ tON
Toff Dly
Toff Dly
+ 5ms
Vmem
Vmem
DLY(MEM)
Vref=1.8V
Vmem=0.9V
Vref=1.8V
Vmem=0.8V
+ 10ms
FN6852.4
(EQ. 13)
(EQ. 14)