ADV202-ASD-P160-EB Analog Devices Inc, ADV202-ASD-P160-EB Datasheet - Page 14

• Manufacturer Part Number: ADV202-ASD-P160-EB
• Manufacturer: Analog Devices Inc

Specifications of ADV202-ASD-P160-EB

• Lead Free Status / Rohs Status: Not Compliant

ADV202
EXTERNAL DMA MODE—FIFO READ, BURST MODE
Table 9.
Parameter
DREQ
t
t
t
t
RD
RD
t
1
2
3
DREQ RTN
DACK SU
RD
HD
DREQ WAIT
Applies to assigned DMA channel, if EDMOD0 or EDMOD1[14:11] is programmed to a value that is not 0. Pulse width depends on the value programmed.
For a definition of JCLK, see the PLL section.
If sufficient space is available in FIFO.
LO
HI
PULSE
HDATA
HDATA
DREQ
DACK
DREQ
DACK
WEFB
RD
Description
DREQ Pulse Width
RD to DREQ Deassert (DR × PULS = 0)
DACK to RD Setup
RD to Data Valid
Data Hold
RD Assert Pulse Width
RD Deassert Pulse Width
Last Burst Access to Next DREQ
Figure 16. Burst Read Cycle for DREQ / DACK DMA Mode for Assigned DMA Channel
DREQ
1
t
RD
PULSE
t
t
t
SU
t
DACKSU
DREQRTN
DACKSU
0
0
(EMOD0/EDMOD1[14:11] NOT Programmed to a Value of 0)
t
t
HD
HD
Figure 15. Burst Write Cycle for Fly-By DMA Mode
( DREQ Pulse Width Is Programmable)
1
1
Rev. C | Page 14 of 40
WE
RD
LO
LO
13
13
Min
1
2.5
0
2.5
2.5
1.5
1.5
2.5
14
14
Typ
WE
RD
HI
HI
Max
15
3.5 × JCLK + 7.5 ns
9.7
3.5 × JCLK + 7.5 ns
15
15
t
t
DREQWAIT
DREQWAIT
3
Unit
JCLK cycles
JCLK cycles
ns
ns
ns
JCLK cycles
JCLK cycles
JCLK cycles
2