ADV202-ASD-P160-EB Analog Devices Inc, ADV202-ASD-P160-EB Datasheet - Page 17

• Manufacturer Part Number: ADV202-ASD-P160-EB
• Manufacturer: Analog Devices Inc

Specifications of ADV202-ASD-P160-EB

• Lead Free Status / Rohs Status: Not Compliant

VDATA MODE TIMING
Table 11.
Parameter
VDATA
VDATA
VDATA
HSYNC
HSYNC
HSYNC
VSYNC
VSYNC
VSYNC
FIELD
FIELD
FIELD
SYNC DELAY
SU
HD
TD
TD
SU
HD
VDATA(OUT)
VDATA(OUT)
VDATA(OUT)
SU
HD
TD
SU
HD
TD
VDATA(IN)
VDATA(IN)
HSYNC
HSYNC
VSYNC
VSYNC
VCLK
VCLK
VCLK
VCLK
VCLK
Description
VCLK to VDATA Valid Delay (VDATA Output)
VDATA Setup to Rising VCLK (VDATA Input)
VDATA Hold from Rising VCLK (VDATA Input)
HSYNC Setup to Rising VCLK
HSYNC Hold from Rising VCLK
VCLK to HSYNC Valid Delay
VSYNC Setup to Rising VCLK
VSYNC Hold from Rising VCLK
VCLK to VSYNC Valid Delay
FIELD Setup to Rising VCLK
FIELD Hold from Rising VCLK
VCLK to FIELD Valid
Decode Data Sync Delay for HD Input with EAV/SAV Codes
Decode Data Sync Delay for SD Input with EAV/SAV Codes
Decode Data Sync Delay for HVF Input (from First Rising VCLK after HSYNC Low to
First Data Sample)
ENCODE CCIR-656 LINE
DECODE MASTER CCIR-656 LINE
DECODE SLAVE CCIR-656 LINE
DECODE SLAVE HVF MODE
ENCODE HVF MODE
*HSYNC AND VSYNC DO NOT HAVE TO BE APPLIED SIMULTANEOUSLY
Cr
Y
Y
Cb
Cr
Y
Cr
Cr
VDATA
Y
VDATA
VDATA
Y
Y
Y
Cb
Cr
VDATA
VDATA
TD
TD
Cb
Cb
SU
Cb
Y
TD
HD
Y
Y
Cb
Y
Y
FF
Cr
FF
Y
FF
Y
Cb
Figure 21. Video Mode Timing
Rev. C | Page 17 of 40
EAV
Y
EAV
EAV
VSYNC
HSYNC
VSYNC
HSYNC
SYNC DELAY
SYNC DELAY
HD
SU
SU
HD
FF
*
*
FF
Cb
SAV
FF
Cb
HSYNC
VSYNC
Y
Cb
SAV
HD
Y
HD
Min
4
4
3
4
3
4
4
3
Cr
Y
Cb
Cr
SAV
Y
Typ
7
9
10
Cr
Y
Y
Cb
Cb
Max
12
12
12
12
Cr
Cb
Y
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VCLK cycles
VCLK cycles
VCLK cycles
ADV202