ATTINY12-8SU Atmel, ATTINY12-8SU Datasheet - Page 18

• Manufacturer Part Number: ATTINY12-8SU
• Description: Microcontrollers (MCU) AVR 1K FLASH 64B EE 5V 8MHZ
• Manufacturer: Atmel

Specifications of ATTINY12-8SU

• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500
• Minimum Operating Temperature: - 40 C
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SPI
• # I/os (max): 6
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC EIAJ
• Lead Free Status / Rohs Status: Details

Register Description
EEPROM Address Register –
EEAR
EEPROM Data Register –
EEDR
EEPROM Control Register –
EECR
18
ATtiny11/12
The EEPROM Address Register – EEAR specifies the EEPROM address in the 64-byte
EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 63.
During reset, the EEAR register is not cleared. Instead, the data in the register is kept.
• Bits 7..0 - EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR register contains the data to be written to
the EEPROM in the address given by the EEAR register. For the EEPROM read opera-
tion, the EEDR contains the data read out from the EEPROM at the address given by
EEAR.
• Bit 7..4 - Res: Reserved Bits
These bits are reserved bits in the ATtiny12 and will always read as zero.
• Bit 3 - EERIE: EEPROM Ready Interrupt Enable
When the I-bit in SREG and EERIE are set (one), the EEPROM Ready interrupt is
enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready interrupt
generates a constant interrupt when EEWE is cleared (zero).
• Bit 2 - EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be
written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at the
selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE
has been set (one) by software, hardware clears the bit to zero after four clock cycles.
See the description of the EEWE bit for a EEPROM write procedure.
• Bit 1 - EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When
address and data are correctly set up, the EEWE bit must be set to write the value into
the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE,
Bit
$1E
Read/Write
Initial Value
Bit
$1D
Read/Write
Initial Value
Bit
$1C
Read/Write
Initial Value
MSB
R/W
R
R
7
0
7
0
7
0
-
-
R/W
R
R
6
0
6
0
6
0
-
-
EEAR5
R/W
R/W
X
R
5
5
0
5
0
-
EEAR4
R/W
R/W
X
R
4
4
0
4
0
-
EEAR3
EERIE
R/W
R/W
R/W
X
3
3
0
3
0
EEMWE
EEAR2
R/W
R/W
R/W
X
2
2
0
2
0
EEAR1
EEWE
R/W
R/W
R/W
X
1
1
0
1
X
EEAR0
EERE
LSB
R/W
R/W
R/W
X
0
0
0
0
0
1006F–AVR–06/07
EECR
EEAR
EEDR