ATTINY12-8SU Atmel, ATTINY12-8SU Datasheet - Page 52

• Manufacturer Part Number: ATTINY12-8SU
• Description: Microcontrollers (MCU) AVR 1K FLASH 64B EE 5V 8MHZ
• Manufacturer: Atmel

Specifications of ATTINY12-8SU

• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500
• Minimum Operating Temperature: - 40 C
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: SPI
• # I/os (max): 6
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC EIAJ
• Lead Free Status / Rohs Status: Details

Figure 27. High-voltage Serial Programming Waveforms
Table 23. High-voltage Serial Programming Instruction Set for ATtiny11/12
52
Instruction
Chip Erase
Write Flash
High and Low
Address
Write Flash Low
byte
Write Flash
High byte
Read Flash
High and Low
Address
Read Flash
Low byte
Read Flash
High byte
Write EEPROM
Low Address
(ATtiny12)
Write EEPROM
byte (ATtiny12)
Read EEPROM
Low Address
(ATtiny12)
SERIAL DATA OUTPUT
SERIAL CLOCK INPUT
SERIAL INSTR. INPUT
SERIAL DATA INPUT
ATtiny11/12
XTAL1/PB3
PB0
PB1
PB2
PB0
PB1
PB2
PB0
PB1
PB2
PB0
PB1
PB2
PB0
PB1
PB2
PB0
PB1
PB2
PB0
PB1
PB2
PB0
PB1
PB2
PB0
PB1
PB2
PB0
PB1
PB2
PB0
PB1
PB2
0_1000_0000_00
0_0100_1100_00
0_0001_0000_00
0_0100_1100_00
0_ i i i i_i i i i _00
0_0010_1100_00
0_ i i i i_i i i i _00
0_0011_1100_00
0_0000_0010_00
0_0100_1100_00
0_0000_0000_00
0_0110_1000_00
0_0000_0000_00
0_0111_1000_00
0_0001_0001_00
0_0100_1100_00
0_ i i i i_i i i i _00
0_0010_1100_00
0_0000_0011_00
0_0100_1100_00
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
Instr.1
0
MSB
MSB
MSB
1
o_oooo_ooox_xx
o_oooo_ooox_xx
0_00bb_bbbb_00
0_00bb_bbbb_00
0_0000_0000_00
0_0110_0100_00
0_0000_000a_00
0_0001_1100_00
0_0000_0000_00
0_0110_0100_00
0_0000_0000_00
0_0111_0100_00
0_0000_000a_00
0_0001_1100_00
0_0000_0000_00
0_0110_1100_00
0_0000_0000_00
0_0111_1100_00
0_0000_1100_00
0_0000_0000_00
0_0110_0100_00
0_0000_1100_00
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
Instr.2
2
Instruction Format
3
0_bbbb_bbbb_00
0_bbbb_bbbb_00
0_0000_0000_00
0_0110_1100_00
0_0000_1100_00
0_0000_0000_00
0_0110_1100_00
0_0000_0000_00
0_0000_0000_00
0_0111_1100_00
0_0000_0000_00
0_0000_1100_00
0_0000_0000_00
0_0110_1100_00
0_0000_0000_00
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
x_xxxx_xxxx_xx
4
Instr.3
5
6
0_0000_0000_00
0_0100_1100_00
x_xxxx_xxxx_xx
Instr.4
7
LSB
LSB
LSB
8
Operation Remarks
Wait after Instr.4 until PB2 goes
high for the Chip Erase cycle to
finish.
Repeat Instr.2 for a new 256 byte
page. Repeat Instr.3 for each new
address.
Wait after Instr.3 until PB2 goes
high. Repeat Instr.1, Instr. 2 and
Instr.3 for each new address.
Wait after Instr.3 until PB2 goes
high. Repeat Instr.1, Instr. 2 and
Instr.3 for each new address.
Repeat Instr.2 and Instr.3 for each
new address.
Repeat Instr.1 and Instr.2 for each
new address.
Repeat Instr.1 and Instr.2 for each
new address.
Repeat Instr.2 for each new
address.
Wait after Instr.3 until PB2 goes
high
Repeat Instr.2 for each new
address.
9
10
1006F–AVR–06/07