LH7A400N0G000B5 NXP Semiconductors, LH7A400N0G000B5 Datasheet - Page 39

• Manufacturer Part Number: LH7A400N0G000B5
• Description: Microcontrollers (MCU) LCD USB FS/HOST MMU ADC BGA256
• Manufacturer: NXP Semiconductors

Specifications of LH7A400N0G000B5

• Data Bus Width: 32 bit
• Program Memory Type: ROMLess
• Data Ram Size: 80 KB
• Interface Type: IrDA, SCI, SPI, SSP, UART, USB
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-256
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Details
• Other names: LH7A400N0G000B5;55

32-Bit System-on-Chip
Synchronous Memory Controller Waveforms
Read (page already open). Figure 15 shows the timing
for Activate a Bank and Write.
SSP Waveforms
data frame formats:
• Texas Instruments SSI
• Motorola SPI
• National Semiconductor MICROWIRE
length, depending upon the programmed data size.
Each data frame is transmitted beginning with the
Most Significant Bit (MSB) i.e. ‘big endian’. For all
three formats, the SSP serial clock is held LOW (inac-
tive) while the SSP is idle. The SSP serial clock tran-
sitions only during active transmission of data. The
SSPFRM signal marks the beginning and end of a
frame. The SSPEN signal controls an off-chip line
driver’s output enable pin.
Preliminary data sheet
Figure 14 shows the timing for a Synchronous Burst
The Synchronous Serial Port (SSP) supports three
Each frame format is between 4 and 16 bits in
Figure 13. External Asynchronous Memory Read with 4 Wait States (BCRx:WST1 = 0b100)
nCS[3:0,
CS[7:6]
D[31:0]
A[27:0]
HCLK
nBLE
nOE
0
1
DATA WOULD BE
LATCHED HERE
0 WAIT STATE,
2
3
VALID ADDRESS
Rev. 01 — 16 July 2007
STATE 1
NXP Semiconductors
WAIT
tWS
nCSx Valid
nBLE Valid
nOE Valid
4
VALID DATA
STATE 2
WAIT
tWS
synchronous serial frame format, Figure 18 through
Figure 25 show the Motorola SPI format, and Figure 26
and Figure 27 show National Semiconductor’s MICRO-
WIRE data frame format.
is pulsed prior to each frame’s transmission for one
serial clock period beginning at its rising edge. For this
frame format, both the SSP and the external slave
device drive their output data on the rising edge of the
clock and latch data from the other device on the falling
edge. See Figure 16 and Figure 17.
5
Figure 16 and Figure 17 show Texas Instruments
For Texas Instruments SSI format, the SSPFRM pin
STATE 3
WAIT
tWS
6
STATE 4
WAIT
tWS
7
8
4 WAIT STATES,
DATA LATCHED
HERE
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