ADV7173KSTZ Analog Devices Inc, ADV7173KSTZ Datasheet - Page 31

• Manufacturer Part Number: ADV7173KSTZ
• Description: IC DAC VIDEO NTSC 6-CH 48LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7173KSTZ

• Applications: Multimedia
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Input Format: Digital
• Output Format: Analog
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Tv / Video Case Style: LQFP
• No. Of Pins: 48
• Msl: MSL 1 - Unlimited
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADV7173EBM - BOARD EVAL FOR ADV7173
• Voltage - Supply, Digital: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

MODE REGISTER 5 MR5 (MR57–MR50)
(Address (SR4-SR0) = 05H)
Mode Register 5 is an 8-bit-wide register. Figure 49 shows the
various operations under the control of Mode Register 5.
MR5 BIT DESCRIPTION
Y-Level Control (MR50)
This bit controls the Y output level on the ADV7172/ADV7173.
If this bit is set (“0”), the encoder outputs SMPTE levels when
configured in PAL mode and Betacam levels when configured
in NTSC mode. If this bit is set (“1”), the encoder outputs
Betacam levels when configured in PAL mode and SMPTE
levels when configured in NTSC mode.
UV-Levels Control (MR52–MR51)
These bits control the U and V output levels on the ADV7172/
ADV7173. It is possible to have UV levels with a peak-peak
amplitude of either 700 mV (MR52 + MR51 = “01”) or 1000 mV
(MR52 + MR51 = “10”) in NTSC and PAL. It is also possible
to have default values of 934 mV for NTSC and 700 mV for
PAL (MR52 + MR51 = “00”).
MR57
0
1
CLAMP POSITION
FRONT PORCH
BACK PORCH
MR57
MR56
CLAMP DELAY
0
1
DIRECTION
MR56
POSITIVE
NEGATIVE
MR55 MR54
0
0
1
1
MR55
CLAMP DELAY
0
1
0
1
NO DELAY
1
2
3
MR54
PCLK
PCLK
PCLK
MR53
0
1
RGB Sync (MR53)
This bit is used to set up the RGB outputs with the sync infor-
mation encoded on all RGB outputs.
Clamp Delay (MR55–MR54)
These bits control the delay or advance of the CLAMP signal in
the front or back porch of the ADV7172/ADV7173. It is possible
to delay or advance the pulse by 0, 1, 2 or 3 clock cycles.
Clamp Delay Direction (MR56)
This bit controls a positive or negative delay in the CLAMP
signal. If this bit is set (“1”), the delay is negative. If it is not set
(“0”), the delay is positive.
Clamp Position (MR57)
This bit controls the position of the CLAMP signal. If this bit is
set (“1”), the CLAMP signal is located in the back porch posi-
tion. If this bit is set to (“0”), the CLAMP signal is located in
the front porch position.
SYNC
MR53
RGB
DISABLE
ENABLE
MR52 MR51
0
0
1
1
UV-LEVELS CONTROL
MR52
0
1
0
1
DEFAULT LEVELS
700mV
1000mV
RESERVED
MR51
MR50
0
1
CONTROL
Y-LEVEL
ADV7172/ADV7173
MR50
DISABLE
ENABLE