ADV7184BSTZ Analog Devices Inc, ADV7184BSTZ Datasheet - Page 90

• Manufacturer Part Number: ADV7184BSTZ
• Description: IC DECODER VID SDTV MULTI 80LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7184BSTZ

• Applications: Projectors, Recorders, Security
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Resolution (bits): 10bit
• Adc Sample Rate: 54MSPS
• Power Dissipation Pd: 550mW
• No. Of Input Channels: 12
• Supply Voltage Range: 1.65V To 2V, 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Tv /: RoHS Compliant
• Input Format: Analogue
• Output Format: Digital
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7184
Address
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
Register
Vsync Field
Control 1
Vsync Field
Control 2
Vsync Field
Control 3
Hsync Position
Control 1
Hsync Position
Control 2
Hsync Position
Control 3
Polarity
NTSC Comb Control
Bit Description
Reserved.
HVSTIM. This bit selects where within a line of
video the VS signal is asserted.
NEWAVMODE. Sets the EAV/SAV mode.
Reserved.
Reserved.
VSBHE.
VSBHO.
Reserved.
VSEHE.
VSEHO.
HSE [10:8]. HS end. These bits allow the posi-
tioning of the HS output within the video line.
Reserved.
HSB [10:8]. HS begin. These bits allow the posi-
tioning of the HS output within the video line.
Reserved.
HSB [7:0]. Using HSB [10:0] and HSE [10:0]
(see Register 0x34), the user can program the
position and length of the HS output signal.
HSE [7:0]. See Registers 0x34 and 0x35.
PCLK. Sets the polarity of LLC.
Reserved.
PF. Sets the FIELD polarity.
Reserved.
PVS. Sets the VS polarity.
Reserved.
PHS. Sets the HS polarity.
YCMN [2:0]. Luma comb mode NTSC.
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7 6 5 4 3 2 1 0 Comments
0 0 0
0
1
0
1
0
0 0 0 0 0 0 1 0
0 0 0 0 0 0 0 0
0
1
0
1
0
1
0 0 0
0
0 0 0 0 0 1 Set to default
0 0 0 1 0 0 Set to default
0
1
0
1
0
Bit
0
1
0
0
1
1
0 1 0 Set to default
0 0 0 HS output ends HSE [10:0] pixels
0 0
0 0 0 Adaptive 3-line, 3-tap luma
1 0 0 Use low-pass notch
1 0 1 Fixed luma comb (two lines)
1 1 0 Fixed luma comb (three lines)
1 1 1 Fixed luma comb (two lines)
0 Invert polarity
1 Normal polarity, as per the timing
Start of line relative to HSE
Start of line relative to HSB
EAV/SAV codes generated to suit
ADI encoders
Manual VS/FIELD position
controlled by Registers 0x32, 0x33,
and 0xE5 to 0xEA
Set to default
VS goes high in the middle of the
line (even field)
VS changes state at the start of the
line (even field)
VS goes high in the middle of the
line (odd field)
VS changes state at the start of the
line (odd field)
VS goes low in the middle of the
line (even field)
VS changes state at the start of the
line (even field)
VS goes low in the middle of the
line (odd field)
VS changes state at the start of the
line (odd field)
after the falling edge of hsync
Set to 0
HS output starts HSB [10:0] pixels
after the falling edge of hsync
Set to 0
diagrams (
4
Set to 0
Active high
Active low
Set to 0
Active high
Active low
Set to 0
Active high
Active low
)
Figure 2
to
Figure
Notes
HSE = hsync end.
HSB = hsync begin.
NEWAVMODE bit must be set high.
NEWAVMODE bit must be set high.
Using HSB and HSE, the user can
program the position and length of
the output hsync.
Sets the polarity of LLC on both LLC1
and LLC2.
Top lines of memory.
All lines of memory.
Bottom lines of memory.