ADV7188BSTZ Analog Devices Inc, ADV7188BSTZ Datasheet - Page 97

• Manufacturer Part Number: ADV7188BSTZ
• Description: IC DECODER VID MULTIFORM 80LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7188BSTZ

• Applications: Set-Top Boxes, Video Players, Recorders
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Resolution (bits): 12bit
• Input Format: Analog
• Output Format: Digital
• Adc Sample Rate: 54MSPS
• No. Of Input Channels: 12
• Supply Voltage Range: 3V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Address
0xEE
0xEF
0xF0
0xF1
0xF3
Register
FB_CONTROL 2
FB_CONTROL 3
FB_CONTROL 4
FB_CONTROL 5
AFE_CONTROL 1
Bit Description
MAN_ALPHA_VAL [6:0]. These bits determine
in what proportion the video from the CVBS
and RGB sources are blended.
FB_CSC_MAN.
FB_EDGE_SHAPE [2:0].
CNTR_ENABLE.
FB_SP_ADJUST.
FB_DELAY [3:0].
Reserved.
RGB_IP_SEL.
Reserved.
CNTR_MODE [1:0]. These bits allow adjustment
of contrast level in the contrast reduction box.
FB_LEVEL [1:0]. These bits control reference
level for fast blank comparator.
CNTR_LEVEL [1:0]. These bits control reference
level for contrast reduction comparator.
AA_FILT_EN [0].
AA_FILT_EN [1].
AA_FILT_EN [2].
AA_FILT_EN [3].
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7 6 5 4 3 2 1 0 Comments
0
1
0 1 0 0
0 1 0 0
0 0
0 1
1 0
1 1
0 0 0 0 0 0 0
0 0
0 1
1 0
1 1
Bit
0
1
0 1 0 0 Delay on FB signal in 28.63636 MHz
0 0
0 1
1 0
1 1
0
1
1
0 0 0 No edge shaping
0 0 1 Level 1 edge shaping
0 1 0 Level 2 edge shaping
0 1 1 Level 3 edge shaping
1 0 0 Level 4 edge shaping
0
1
0
0
1
0 SD RGB input for FB on AIN7, AIN8,
1 SD RGB input for FB on AIN4, AIN5,
0 Disables the internal antialiasing
1 Enables the internal antialiasing
Automatic configuration of the
CSC for SCART support
Enable manual programming of CSC
Contrast reduction mode disabled
and FB signal interpreted as
bilevel signal
Contrast reduction mode enabled
and FB signal interpreted as
trilevel signal
Adjusts FB timing in reference to
the sampling clock
clock cycles
and AIN9
and AIN6
Set to 0
25%
50%
75%
100%
CNTR_ENABLE = 0,
FB threshold = 1.4 V
CNTR_ENABLE = 1,
FB threshold = 1.6 V
CNTR_ENABLE = 0,
FB threshold = 1.6 V
CNTR_ENABLE = 1,
FB threshold = 1.8 V
CNTR_ENABLE = 0,
FB threshold = 1.8 V
CNTR_ENABLE = 1,
FB threshold = 2 V
CNTR_ENABLE = 0,
FB threshold = 2 V
CNTR_ENABLE = 1,
FB threshold = not used
0.4 V contrast reduction threshold
0.6 V contrast reduction threshold
0.8 V contrast reduction threshold
Not used
filter on Channel 0
filter on Channel 0
Disables the internal antialiasing
filter on Channel 1
Enables the internal antialiasing
filter on Channel 1
Disables the internal antialiasing
filter on Channel 2
Enables the internal antialiasing
filter on Channel 2
Disables the internal antialiasing
filter on Channel 3
Enables the internal antialiasing
filter on Channel 3
Notes
CSC is used to convert RGB portion of
SCART signal to YCrCb
Improves picture transition for high
speed fast blank switching. All other
settings are invalid.
Each LSB corresponds to ⅛
clock cycle
CNTR_ENABLE = 1
ADV7188
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