ADV7321KSTZ Analog Devices Inc, ADV7321KSTZ Datasheet - Page 61

• Manufacturer Part Number: ADV7321KSTZ
• Description: IC VID ENC 6-12BIT DAC'S 64LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7321KSTZ

• Applications: EVD, DVD, SD/PS/HDTV
• Voltage - Supply, Analog: 2.5V
• Voltage - Supply, Digital: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Input Format: Digital
• Output Format: Analog
• Supply Voltage Range: 2.375V To 2.625V
• Operating Temperature Range: 0°C To +70°C
• Tv / Video Case Style: LQFP
• No. Of Pins: 64
• Msl: MSL 1 - Unlimited
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

HSYNC/VSYNC OUTPUT CONTROL
The ADV7320/ADV7321 have the ability to accept either embedded time codes in the input data, or external Hsync and Vsync signals on
P_HSYNC / P_VSYNC , outputting the respective signals on the S_HSYNC and S_VSYNC pins.
Table 36. Hsync Output Control
HD/ED
Slave Mode
(0x10, Bit 2)
x
x
External Hsync and
Vsync/Field Mode
EAV/SAV Mode
x
1
2
Table 37. Vsync Output Control
HD/ED
Slave Mode
(0x10, Bit 2)
x
x
External Hsync and
Vsync/Field Mode
EAV/SAV Mode
EAV/SAV Mode
x
x
1
2
In all HD/ED standards where there is an Hsync o/p, the start of the Hsync pulse is aligned with the falling edge of the embedded Hsync in the output video.
ED = enhanced definition.
In all HD/ED standards where there is an Hsync o/p, the start of the Hsync pulse is aligned with the falling edge of the embedded Hsync in the output video.
ED = enhanced definition = progressive scan 525p or 625p.
2
2
HD/ED Sync
Output Enable
(0x02, Bit 7)
0
0
1
1
1
1
1
HD/ED Sync
Output Enable
(0x02, Bit 7)
0
0
1
1
1
1
1
SD Sync
Output Enable
(0x02, Bit 6)
0
1
x
x
x
x
x
SD Sync
Output Enable
(0x02, Bit 6)
0
1
x
x
x
I2C_Vsync _gen_sel
(0x14, Bit 2)
x
x
0
0
0
1
1
Rev. A | Page 61 of 88
I2C_Hsync_gen_sel
(0x14, Bit 1)
x
x
0
0
1
Video Standard
x
Interlaced
x
All HD interlace
standards
All HD/ED
progressive
standards
All HD/ED stan-
dards except
525p
525p
Signal on S_HSYNC Pin
Tristate
Pipelined SD Hsync
External Pipelined HD/ED
Hsync
Pipelined HD/ED Hsync based
on AV Code H bit
Pipelined HD/ED Hsync
based on horizontal counter
Signal on
S_VSYNC Pin
Tristate
Pipelined SD
Vsync/field
External pipelined
HD/ED Vsync or
field signal
External pipelined
field signal based
on AV Code F bit
Pipelined Vsync
based on AV
Code V bit
External pipelined
HD/ED Vsync based
on vertical counter
External pipelined
HD/ED VSYNC
based on vertical
counter
ADV7320/ADV7321
Duration
–
See Appendix 5—
SD Timing Modes
As per Hsync
timing
Same as line
blanking interval
Same as
embedded Hsync
Duration
–
See Appendix
5—SD Timing
Modes
As per external
Vsync or field
signal
Field
Vertical
blanking
interval
Aligned with
serration lines
Vertical
blanking
interval