ADV7321KSTZ Analog Devices Inc, ADV7321KSTZ Datasheet - Page 72
![IC VID ENC 6-12BIT DAC'S 64LQFP](/photos/6/60/66065/505-64-lqfp_sml.jpg)
ADV7321KSTZ
Manufacturer Part Number
ADV7321KSTZ
Description
IC VID ENC 6-12BIT DAC'S 64LQFP
Manufacturer
Analog Devices Inc
Type
Video Encoderr
Datasheet
1.ADV7321KSTZ.pdf
(88 pages)
Specifications of ADV7321KSTZ
Applications
EVD, DVD, SD/PS/HDTV
Voltage - Supply, Analog
2.5V
Voltage - Supply, Digital
2.5V
Mounting Type
Surface Mount
Package / Case
64-LQFP
Input Format
Digital
Output Format
Analog
Supply Voltage Range
2.375V To 2.625V
Operating Temperature Range
0°C To +70°C
Tv / Video Case Style
LQFP
No. Of Pins
64
Msl
MSL 1 - Unlimited
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADV7321KSTZ
Manufacturer:
Micrel
Quantity:
2 023
Company:
Part Number:
ADV7321KSTZ
Manufacturer:
ADI
Quantity:
329
Company:
Part Number:
ADV7321KSTZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADV7321KSTZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
ADV7320/ADV7321
The register settings in Table 41 are used to generate an SD NTSC
CVBS output on DAC A, S-video on DACs B and C, and YPrPb
on DACs D, E, and F. Upon power-up, the subcarrier registers
are programmed with the appropriate values for NTSC. All
other registers are set as normal/default.
Table 41. NTSC Test Pattern Register Writes
Subaddress
0x00
0x40
0x42
0x44
0x4A
For PAL CVBS output on DAC A, the same settings are used,
except Subaddress 0x40 is programmed to 0x11 and the F
registers are programmed as shown in Table 42.
Table 42. PAL F
Subaddress
0x4C
0x4D
0x4E
0x4F
Note that when programming the F
write the values in the sequence F
F
SC
value is only accepted after the F
SC
Description
F
F
F
F
Register Writes
SC
SC
SC
SC
0
1
2
3
Register Setting
0xFC
0x10
0x40
0x40 (internal test pattern on)
0x08
SC
0, F
SC
SC
3 write is complete.
registers, the user must
SC
1, F
Register Setting
0xCB
0x8A
0x09
0x2A
SC
2, F
SC
3. The full
SC
Rev. A | Page 72 of 88
The register settings in Table 43 are used to generate a 525p
hatch pattern on DAC D, E, and F. All other registers are set as
normal/default.
Table 43. 525p Test Pattern Register Writes
Subaddress
Ox00
0x01
0x10
0x11
0x16
0x17
0x18
For 625p hatch pattern on DAC D, the same register settings are
used except Subaddress 0x10 = 0x18.
Register Setting
0xFC
0x10
0x00
0x05
0xA0
0x80
0x80