ADV7183AKST Analog Devices Inc, ADV7183AKST Datasheet - Page 24

no-image

ADV7183AKST

Manufacturer Part Number
ADV7183AKST
Description
IC VIDEO DECODER NTSC 80-LQFP
Manufacturer
Analog Devices Inc
Type
Video Decoderr
Datasheet

Specifications of ADV7183AKST

Applications
Projectors, Recorders, Security
Voltage - Supply, Analog
3.15 V ~ 3.45 V
Voltage - Supply, Digital
1.65 V ~ 2 V
Mounting Type
Surface Mount
Package / Case
80-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADV7183AKST
Manufacturer:
AD
Quantity:
1 831
Part Number:
ADV7183AKST
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
ADV7183AKST
Quantity:
2 000
Part Number:
ADV7183AKSTZ
Manufacturer:
ON
Quantity:
2 876
ADV7183A
Lock Related Controls
Lock information is presented to the user through Bits [1:0] of
the Status 1 register. See the STATUS_1[7:0] Address 0x10 [7:0]
section. Figure 9 outlines the signal flow and the controls
available to influence the way the lock status information is
generated.
SRLS Select Raw Lock Signal, Address 0x51 [6]
Using the SRLS bit, the user can choose between two sources for
determining the lock status (per Bits [1:0] in the Status 1 register).
Table 40. SRLS Function
SRLS
0 (default)
1
FSCLE F
The FSCLE bit allows the user to choose whether the status of
the color subcarrier loop is taken into account when the overall
lock status is determined and presented via Bits [1:0] in Status
Register 1. This bit must be set to 0 when operating the
ADV7183A in YPrPb component mode in order to generate a
reliable HLOCK status bit.
Table 41. FSCLE Function
FSCLE
0
1 (default)
The time_win signal is based on a line-to-line evaluation of
the horizontal synchronization pulse of the incoming
video. It reacts quite quickly.
The free_run signal evaluates the properties of the
incoming video over several fields, and takes vertical
synchronization information into account.
SC
Lock Enable, Address 0x51 [7]
Description
Overall lock status only dependent on
horizontal sync lock.
Overall lock status dependent on horizontal
sync lock and F
Description
Select the free_run signal.
Select the time_win signal.
FREE_RUN
TIME_WIN
F
SC
TAKE F
LOCK
SC
Lock.
SC
LOCK INTO ACCOUNT
1
0
SELECT THE RAW LOCK SIGNAL
SRLS
FSCLE
Figure 9. Lock Related Signal Path
0
1
Rev. B | Page 24 of 104
COUNTER OUT OF LOCK
COUNTER INTO LOCK
FILTER THE RAW LOCK SIGNAL
CIL[2:0], COL[2:0]
CIL[2:0] Count Into Lock, Address 0x51 [2:0]
CIL[2:0] determines the number of consecutive lines for which
the into lock condition must be true before the system switches
into the locked state, and reports this via Status 0 [1:0].
Table 42. CIL Function
CIL[2:0]
000
001
010
011
100 (default)
101
110
111
COL[2:0] Count Out of Lock, Address 0x51 [5:3]
COL[2:0] determines the number of consecutive lines for which
the out of lock condition must be true before the system
switches into unlocked state, and reports this via Status 0 [1:0].
Table 43. COL Function
COL[2:0]
000
001
010
011
100 (default)
101
110
111
MEMORY
Description (Count Value in Lines of Video)
1
2
5
10
100
500
1000
100000
Description (Count Value in Lines of Video)
1
2
5
10
100
500
1000
100000
STATUS 1 [0]
STATUS 1 [1]

Related parts for ADV7183AKST