ADV7183AKST Analog Devices Inc, ADV7183AKST Datasheet - Page 64

• Manufacturer Part Number: ADV7183AKST
• Description: IC VIDEO DECODER NTSC 80-LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7183AKST

• Applications: Projectors, Recorders, Security
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADV7183A
REGISTER ACCESSES
The MPU can write to or read from all of the ADV7183A’s
registers, except those registers that are read-only or write-only.
The Subaddress register determines which register the next read
or write operation accesses. All communications with the part
through the bus start with an access to the Subaddress register.
Then, a read/write operation is performed from/to the target
address, which then increments to the next address until a stop
command on the bus is performed.
REGISTER PROGRAMMING
The following section describes each register in terms of its
configuration. The Communications register is an 8-bit, write-
only register. After the part has been accessed over the bus and
a read/write operation is selected, the subaddress is set up. The
Subaddress register determines to/from which register the
operation takes place. Table 170 lists the various operations
under the control of the Subaddress register for the control
port.
Register Select (SR7–SR0)
These bits are set up to point to the required starting address.
Rev. B | Page 64 of 104
I
An I
exceeds eight bits, and is therefore distributed over two or more
I
When such a parameter is changed using two or more I
operations, the parameter may hold an invalid value for the
time between the first I
completed. In other words, the top bits of the parameter may
already hold the new value while the remaining bits of the
parameter still hold the previous value.
To avoid this problem, the I
updated bits of the parameter in local memory; all bits of the
parameter are updated together once the last register write
operation has completed.
The correct operation of the I
following:
•
•
2
2
C registers, for example, HSB [11:0].
C SEQUENCER
2
All I
written to in order of ascending addresses, for example, for
HSB[10:0], write to Address 0x34 first, followed by 0x35.
No other I
writes for the sequence, for example, for HSB[10:0], write
to Address 0x34 first, immediately followed by 0x35.
C sequencer is employed in cases where a parameter
2
C registers for the parameter in question must be
2
C taking place between the two (or more) I
2
C finishing and the last I
2
C sequencer holds the already
2
C sequencer relies on the
2
C being
2
C write
2
C