ADV7183AKST Analog Devices Inc, ADV7183AKST Datasheet - Page 50

• Manufacturer Part Number: ADV7183AKST
• Description: IC VIDEO DECODER NTSC 80-LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7183AKST

• Applications: Projectors, Recorders, Security
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADV7183A
Table 129. PVENDSIGN Function
PVENDSIGN
0 (default)
1
PVEND[4:0] PAL VSync End, Address 0xE9 [4:0]
Table 130. PVEND Function
PVEND
10100 (default)
For all NTSC/PAL VSync timing controls, both the V bit in the
AV code and the VSync on the VS pin are modified.
PFTOGDELO PAL Field Toggle Delay on Odd Field,
Address 0xEA [7]
Table 131. PFTOGDELO Function
PFTOGDELO
0 (default)
1
PFTOGDELE PAL Field Toggle Delay on Even Field,
Address 0xEA [6]
Table 132. PFTOGDELE Function
PFTOGDELE
0
1 (default)
PFTOGSIGN PAL Field Toggle Sign, Address 0xEA [5]
Table 133. PFTOGSIGN Function
PFTOGSIGN
0
1 (default)
PFTOG PAL Field Toggle, Address 0xEA [4:0]
Table 134. PFTOG Function
PFTOG
00011 (default)
For all NTSC/PAL Field timing controls, the F bit in the AV
code and the Field signal on the FIELD/DE pin are modified.
PVENDSIGN PAL VSync End Sign, Address 0xE9 [5]
PAL Field toggle position.
Description
Delay end of VSync. Set for user manual
programming.
Advance end of VSync. Not recommended for
user programming.
Description
PAL VSync end position.
Description
No delay.
Delay F toggle/transition on an odd field by a
line relative to PFTOG.
Description
No delay.
Delay F toggle/transition on an even field by
a line relative to PFTOG.
Description
Delay Field transition. Set for user manual
programming.
Advance Field transition. Not recommended
for user programming.
Description
Rev. B | Page 50 of 104
SYNC PROCESSING
The ADV7183A has two additional sync processing blocks that
postprocess the raw synchronization information extracted from
the digitized input video. If desired, the blocks can be disabled
via the following two I
ENHSPLL Enable HSync Processor, Address 0x01 [6]
The HSync processor is designed to filter incoming HSyncs that
have been corrupted by noise, providing improved performance
for video signals with stable time bases but poor SNR.
For CVBS PAL/NTSC, YC PAL/NTSC enable the HSync pro-
cessor. For SECAM disable the HSync processor. For YPrPb,
disable HSync processor.
Table 135. ENHSPLL Function
ENHSPLL
0
1 (default)
ENVSPROC Enable VSync Processor, Address 0x01 [3]
This block provides extra filtering of the detected VSyncs to
give improved vertical lock.
Table 136. ENVSPROC Function
ENVSPROC
0
1 (default)
NOT VALID FOR USER
PROGRAMMING
ADVANCE TOGGLE OF
FIELD BY PTOG[4:0]
Description
Disable VSync processor.
Enable VSync processor.
PFTOGDELO
ADDITIONAL
DELAY BY
1 LINE
YES
Description
Disable the HSync processor.
Enable the HSync processor.
1
2
Figure 30. PAL F Toggle
C bits.
1
0
PFTOGSIGN
ODD FIELD?
TOGGLE
FIELD
0
FIELD BY PFTOG[4:0]
DELAY TOGGLE OF
PFTOGDELE
ADDITIONAL
DELAY BY
0
1 LINE
NO
1