HSP43220JC-25Z Intersil, HSP43220JC-25Z Datasheet - Page 6

• Manufacturer Part Number: HSP43220JC-25Z
• Description: IC DECIMATING DGTL FILTER 84PLCC
• Manufacturer: Intersil

Specifications of HSP43220JC-25Z

• Filter Type: Digital
• Number Of Filters: 4
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency - Cutoff Or Center: -
• Max-order: -

DDF Control Registers
F_Register (A1 = 0, A0 = 0)
F_OAD
FA0
15
F_BYP
FB0
14
F_ESYM
ES0
13
6
D3 D2 D1 D0 T8 T7 T6 T5 T4 T3 T2 T1 T0
12
F_DRATE
11
10
9
8
7
F_TAPS
Bits T0-T8 are used to specify the number of FIR filter taps. The number
entered is one less than the number of taps required. For example, to
specify a 511 tap filter F_TAPS would be programmed to 510. The
minimum number of FIR taps = 3 (F_TAPS = 2).
F_DRATE
Bits D0-D3 are used to specify the amount of FIR decimation. The
number entered is one less than the decimation required. For example,
to specify decimation of 16, F_DRATE would be programmed to 15. For
no FIR decimation, F_DRATE would be set equal to 0. FDRATE +1 is
defined as F
F_ESYM
Bit ES0 is used to select the FIR symmetry. F_ESYM is set equal to one
to select even symmetry and set equal to zero to select odd symmetry.
When F_ESYM is one, data is added in the pre-adder; when it is zero,
data is subtracted. Normally set to one.
F_BYP
FB0 is used to select FIR bypass mode. FIR bypass mode is selected by
setting F_BYP = 1. When FIR bypass mode is selected, the FIR is
internally set up for a 3 tap even symmetric filter, no decimation
(F_DRATE = 0) and F_OAD is set equal to one to zero one side of the
preadder. In FIR bypass mode all FIR filter parameters, except F_CLA,
are ignored, including the contents of the FIR coefficient RAM. In FIR
bypass mode the output data is brought output on the lower 16 bits of the
output bus DATA_OUT 0-15. To disable FIR bypass mode, F_BYP is set
equal to zero. When F_BYP is returned to zero, the coefficients must be
reloaded.
F_OAD
Bit FA0 is used to select the zero the preadder mode. This mode zeros
one of the inputs to the pre-adder. Zero preadder mode is selected by
setting F_OAD equal to one. This feature is useful when implementing
arbitrary phase filters or can be used to verify the filter coefficients. To
disable the Zero Preadder mode F_OAD is set equal to zero.
HSP43220
6
FIGURE 4.
5
F_TAPS
4
DEC
3
.
2
1
0
October 10, 2008
FN2486.10