HSP43220 Intersil Corporation, HSP43220 Datasheet
HSP43220
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HSP43220 Summary of contents
Page 1
... ICs. This reduction in component count results in faster development times as well as reduction of hardware costs. The HSP43220 is implemented as a two stage filter structure. As seen in the block diagram, the first stage is a high order decimation filter (HDF) which utilizes an efficient sample rate reduction technique to obtain decimation up to 1024 through a coarse low-pass fi ...
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... RDY OUT 23 ENX C _ BUS C _ BUS DATA _ OUT _ V GND OUT 22 ENP OUT_ FIR _ GND SELH BUS HSP43220 13 BOTTOM VIEW C _ BUS PINS DATA _ DATA _ DATA DATA _ DATA _ DATA _ DATA _ DATA _ DATA ...
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... RESET C_BUS15 C_BUS14 C_BUS13 C_BUS12 C_BUS11 C_BUS10 C_BUS9 GND GND C_BUS8 C_BUS7 C_BUS6 NC C_BUS5 C_BUS4 3-196 HSP43220 100 LEAD MQFP TOP VIEW 100 ...
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... DATA_IN0-15 I Input Data Bus. This bus is used to provide the 16-bit input data to the HSP43220. The data must be provided in a synchro- nous fashion, and is latched on the rising edge of the CK_IN signal. The data bus is in 2's complement fractional format. Bit 15 is the MSB. ...
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... ASTARTIN is internally synchronized to CK_IN and is used to generate STARTOUT. STARTOUT O STARTOUT is a pulse generated from the internally synchronized version of ASTARTIN provided as an output for use in multi-chip configurations to synchronously start multiple HSP43220's. The width of STARTOUT is equal to the period of CK_IN. STARTIN I STARTIN is a Synchronous Input ...
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... DECI- MATION REGISTER RESET RESET REG B A-B REG CK_DEC 3-199 HSP43220 0 0 MUX MUX INT_EN4 INT_EN3 REG REG 53 43 FIGURE 2. INTEGRATOR There are three signals that control the Comb Filter; H_ STAGES, H_BYP and RESET. In Figure 3 these control signals are decoded as COMB_EN1 - COMB_EN5. The order of the Comb fi ...
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... 3-200 HSP43220 Clock Divider and Control Logic The clock divider divides CK_IN by the decimation factor H to produce CK_DEC. CK_DEC clocks the Decimation DEC Round Up Register, Comb Filter section, HDF output register. In the Truncate FIR fi ...
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... H_Register 1 ( RESERVED F_DIS F_CLA H_BYP FD0 FC0 3-201 HSP43220 F_CF F_CF Bits C0-C19 represent the coefficient data, where C19 is the MSB. Two writes are required to write each coefficient which is 2's complement fractional format. The first write loads C19 through C4 ...
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... ISTART, for the DDF. When RESET is asserted the internal start signal is held inactive, thus it is necessary to assert either ASTARTIN or STARTIN in order to start the DDF. The timing of the first valid DATA_IN with respect to START_IN is shown in the Timing Waveforms. 3-202 HSP43220 H_GROWTH H_STAGES ...
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... FIR_CK, CK_DEC, the number of taps that can be implemented in the FIR, the decimation rate in the HDF and the decimation rate in the FIR. (In the Design Considerations 3-203 HSP43220 section of the OPERATIONAL SECTION there is a chart that shows the tradeoffs between these parameters.) FIR_CK This equation expresses the minimum FIR_CK ...
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... F_BYP OUT_SELH OUT_ENX DATA_OUT16-23 3-204 HSP43220 output bus, DATA_OUT0-15. The output formatter is shown in detail in Figure 10. FIR Control Logic The DATA_RDY strobe indicates that new data is available on the output of the FIR. The rising edge of DATA_RDY can be used to load the output data into an external register or RAM. ...
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... CK_IN. Internally the DDF then uses this start pulse to put the DDF in operate mode and start accepting data inputs. When STARTIN is used to start the DDF the ASTARTIN input must be tied high to prevent false starts. 3-205 HSP43220 INPUT DATA FORMAT Fractional Two's Complement Input ...
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... ASTARTIN CK_IN FIR_CK Chip Set Application The HSP43220 is ideally suited for narrow band filtering in Communications, Instrumentation and Signal Processing applications. The HSP43220 provides a fully integrated solution to high order decimation filtering. The combination of the HSP43220 and the HSP45116 (which is a NCOM Numerically Controlled Oscillator / Modulator) provides a complete solution to digital receivers ...
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... It also creates all the information necessary to program the DDF, including a PROM file for programming the control registers. 3-207 HSP43220 TABLE 1. DESIGN TRADE OFF FOR MINIMUM ...
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... HSP43220 FIGURE 15. DECIMATE DESIGN MODULE SCREENS 3-208 ...
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... Output Capacitance NOTES: 2. Power supply current is proportional to operating frequency. Typical rating for I 3. Not tested, but characterized at initial design and at major process/design changes. 4. Output load per test load circuit with switch open and C 3-209 HSP43220 o Thermal Information C Thermal Resistance (Typical, Note 1) +0.5V CPGA Package ...
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... Transition is measured at 200mV from steady state voltage with loading as specified in test load circuit with and Testing is performed as follows: Input levels (CLK Input) 4.0V and 0V, Input levels (all other Inputs) 0V and 3.0V, Timing reference levels (CLK) = 2.0V, (Others) = 1.5V, Output load per test load circuit and C 8. Applies only when H_BYP = 1 or H_DRATE = 0. 3-210 HSP43220 +4.75V to +5.25V ...
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... NOTE: Test head capacitance. Timing Waveforms t SET t CLK_IN HOLD DATA_IN FIGURE 16A. t AST ASTARTIN CK_IN STARTOUT CK_IN t STIC t STARTIN HOLD DATA_IN FIGURE 17A. 3-211 HSP43220 S DUT 1 C (NOTE AND I CCSB CCOP EQUIVALENT CIRCUIT FIR_CK t SPWH CLK_IN FIGURE 16. INPUT TIMING RESET t STOD t SET FIGURE 17 ...
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... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 3-212 HSP43220 t DATA_OUT 16-23 FIRDR UPPER 8 BITS OUT_SELH OUT_ENP OUT_ENX t ...