TLE72422GXT Infineon Technologies, TLE72422GXT Datasheet - Page 17

• Manufacturer Part Number: TLE72422GXT
• Manufacturer: Infineon Technologies

Specifications of TLE72422GXT

• Operating Temperature (max): 150C
• Operating Temperature (min): -40C
• Pin Count: 28
• Mounting: Surface Mount
• Screening Level: Automotive
• Lead Free Status / Rohs Status: Compliant

fault is detected. Certain faults can be prevented from activating the FAULT pin by setting the fault mask register
in SPI message #7.
Once a fault is detected it is latched into the FAULT register. The microcontroller can access the FAULT register
by sending SPI message #9.
If the RESET_B line transitions high-to-low, a RL bit is latched into the FAULT register. The register is cleared after
it is read from the SPI. The RL bit in the FAULT register will not be set again until the next high-to-low transition
occurs on the RESET_B pin.
If the ENABLE pin voltage is low, the ENL bit is latched in the FAULT register. The ENL bit is cleared when the
ENABLE pin returns to a high state and the FAULT register is accessed by SPI message #9.
The diagnostic delay timers for the on-state and off-state diagnostic functions are derived from the master clock
signal applied to the pin CLK using a programmable predivider. This predivider is programmable by the DT1 and
DT0 bits in SPI message #7.
Table 1
Three fault types in 4 different fault bits are defined:
The fault bit is 1 if the fault is detected.
Table 2
Fault Type
Short to Ground Fault
Short to Battery Fault
Open Load Fault
Note: In order to differentiate between a Short to Ground Failure and an Open Load Failure, the channel must be
Tested Diagnostic Bits
The tested bits allow the distinction between a true No Fault and a No Fault due to an untested state (the detection
interval has yet to occur). For instance when the calculated duty cycle is too low to complete the short to battery
test.
Data Sheet
turned off (setpoint = 0ma).
DT1
0
0
1
1
Timebase for Diagnostics
Diagnostic Flags / Bits
t
DIAG
DT0
0
1
0
1
_
PERIOD
=
Abr.
SG
SB
OL
n
Pre-divider
fault
*
F
Gate is ON
OL-ON-F reported (=0 in
ON/OFF mode)
Bit SB-F
BIT OL-ON-F
(=0 in ON/OFF mode)
predivider
128
192
192
256
CLK
17
Functional Description and Electrical Characteristics
Tested Timer and Fault Detection Timer
Period.
F
CLK
9
=20 MHz
≤
128 µsec
64 µsec
96 µsec
96 µsec
n
fault
≤
10
Gate is OFF
Bit SG-F
Bit OL-OFF-F
F
CLK
Rev. 1.0, 2008-07-09
=40 MHz
32 µsec
48 µsec
48 µsec
64 µsec
TLE7242-2G