DS1878T+T&R Maxim Integrated Products, DS1878T+T&R Datasheet - Page 17

• Manufacturer Part Number: DS1878T+T&R
• Description: IC CTLR SFP W/DGTL LDD RX 28TQFN
• Manufacturer: Maxim Integrated Products
• Type: SFP+ Controllerr

Specifications of DS1878T+T&R

• Input Type: *
• Output Type: *
• Interface: *
• Current - Supply: *
• Mounting Type: Surface Mount
• Package / Case: 28-WFQFN exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

If the weighting of the ADC digital reading must con-
form to a predetermined full-scale (PFS) value defined
by a standard’s specification (e.g., SFF-8472), then
right-shifting can be used to adjust the PFS analog
measurement range while maintaining the weighting of
the ADC results. The device’s range is wide enough to
cover all requirements; when the maximum input value
is ≤ 1/2 of the FS value, right-shifting can be used to
obtain greater accuracy. For instance, the maximum
voltage might be 1/8 the specified PFS value, so only
1/8 the converter’s range is effective over this range.
An alternative is to calibrate the ADC’s full-scale range
to 1/8 the readable PFS value and use a right-shift
value of 3. With this implementation, the resolution of
the measurement is increased by a factor of 8, and
Figure 5. ADC Round-Robin Timing
Figure 6. MON2 V
Figure 7. MON3 Differential Input for High-Side RSSI
ROSA
1kΩ
NOTE: IF THE VCC LO ALARM IS ENABLED AT POWER-UP, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMPERATURE AND V
IS ABOVE THE V
680Ω
V
SFP+ Controller with Digital LDD Interface
CC
CC
V
BMD
CC
______________________________________________________________________________________
or GND Reference
CC
MON2
ALARM LOW THRESHOLD.
MON3P
MON3N
V
CC
Right-Shifting ADC Result
ONE ROUND-ROBIN ADC CYCLE
TEMP
DS1878
V
CC
ADC
MON1
ADC
t
RR
MON2
because the result is digitally divided by 8 by right-
shifting, the bit weight of the measurement still meets
the standard’s specification (i.e., SFF-8472).
The right-shift operation on the ADC result is carried out
based on the contents of right-shift control registers
(Table 02h, Registers 8Eh–8Fh) in EEPROM. Three ana-
log channels, MON1–MON3, each have 3 bits allocated
to set the number of right-shifts. Up to seven right-shift
operations are allowed and are executed as a part of
every conversion before the results are compared to
the high-alarm and low-alarm levels, or loaded into their
corresponding measurement registers (Lower Memory,
Registers 64h–6Bh). This is true during the setup of
internal calibration as well as during subsequent data
conversions.
The device offers a configurable input for MON2.
MON2 can either be referenced to V
shown in Figure 6. This enables compatibility with dif-
ferent TOSA monitor diode configurations.
The device offers a fully differential input for MON3.
This enables high-side monitoring of RSSI, as shown in
Figure 7. This reduces board complexity by eliminating
the need for a high-side differential amplifier or a cur-
rent mirror.
1kΩ
MON3
V
CC
BMD
MON4
MON2
V
V
CC
CC
TEMP
or GND Referenced MON2 Input
Differential MON3 Input
CC
ONLY UNTIL V
CC
ADC
CC
or GND, as
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