DS1878T+T&R Maxim Integrated Products, DS1878T+T&R Datasheet - Page 61
DS1878T+T&R
Manufacturer Part Number
DS1878T+T&R
Description
IC CTLR SFP W/DGTL LDD RX 28TQFN
Manufacturer
Maxim Integrated Products
Type
SFP+ Controllerr
Datasheet
1.DS1878TTR.pdf
(98 pages)
Specifications of DS1878T+T&R
Input Type
*
Output Type
*
Interface
*
Current - Supply
*
Mounting Type
Surface Mount
Package / Case
28-WFQFN exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Table 02h, Register 89h: CNFGA
89h
FACTORY DEFAULT
READ ACCESS
WRITE ACCESS
MEMORY TYPE
SFP+ Controller with Digital LDD Interface
LOSC
BIT 7
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
______________________________________________________________________________________
LOSC: LOS Configuration. Defines the source for the LOSOUT pin (see Figure 15).
0 = LOS LO alarm is used as the source.
1 = (Default) LOS input pin is used as the source.
RESERVED
INV LOS: Inverts the buffered input pin LOS or LOS LO alarm to output pin LOSOUT (see Figure 15).
0 = Noninverted LOS or LOS LO alarm to LOSOUT pin.
1 = Inverted LOS or LOS LO alarm to LOSOUT pin.
ASEL: Address Select.
0 = Device address is A2h.
1 = Byte DEVICE ADDRESS in Table 02h, Register 8Ch is used as the device address.
MASK:
0 = Alarm-enable row exists at Table 01h, Registers F8h–FFh. Table 05h, Registers F8h–FFh are
empty.
1 = Alarm-enable row exists at Table 05h, Registers F8h–FFh. Table 01h, Registers F8h–FFh are
empty.
INVRSOUT: Allow for inversion of RSELOUT pin (see Figure 15).
0 = RSELOUT is not inverted.
1 = RSELOUT is inverted.
RESERVED
INVTXF: Allow for inversion of signal driven by the TXF input pin.
0 = (Default) TXF signal is not inverted.
1 = TXF signal is inverted.
RESERVED
80h
PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
PW2 or (PW1 and RWTBL246)
Nonvolatile (SEE)
INV LOS
ASEL
MASK
INVRSOUT
RESERVED
INVTXF
BIT 0
61
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