DS1876T+T&R Maxim Integrated Products, DS1876T+T&R Datasheet - Page 48

• Manufacturer Part Number: DS1876T+T&R
• Description: IC CTRLR SFP DUAL LDD 28TQFN
• Manufacturer: Maxim Integrated Products
• Type: SFP Laser Controllerr

Specifications of DS1876T+T&R

• Input Type: Logic
• Output Type: Logic
• Interface: I²C
• Current - Supply: 10mA
• Mounting Type: Surface Mount
• Package / Case: 28-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SFP Controller with Dual LDD Interface
Table 02h, Register 89h: CNFGB
48
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89h
FACTORY DEFAULT
READ ACCESS
WRITE ACCESS
A2h AND B2h MEMORY
MEMORY TYPE
IN1C
BIT 7
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
IN1C: IN1 software control bit (see Figure 10).
0 = IN1 pin’s logic controls OUT1 pin.
1 = OUT1 is active (bit 6 defines the polarity).
INVOUT1: Inverts the active state for OUT1 (see Figure 10).
0 = Noninverted.
1 = Inverted.
ALATCH2: ADC alarm’s comparison latch for transmitter 2. Latches alarms in Lower Memory,
Registers 70h–71h.
0 = ADC alarm and flags reflect the status of the last comparison.
1 = ADC alarm flags remain set.
QTLATCH2: QT’s comparison latch for transmitter 2. Latches QT alarms in Lower Memory,
Registers 72h–73h and 76h.
0 = QT alarm and warning flags reflect the status of the last comparison.
1 = QT alarm and warning flags remain set.
WLATCH2: ADC warning’s comparison latch for transmitter 2. Latches warnings in Lower Memory,
Registers 74h–75h.
0 = ADC warning flags reflect the status of the last comparison.
1 = ADC warning flags remain set.
ALATCH1: ADC alarm’s comparison latch for transmitter 1. Latches alarms in Lower Memory,
Registers 70h–71h.
0 = ADC alarm and flags reflect the status of the last comparison.
1 = ADC alarm flags remain set.
QTLATCH1: QT’s comparison latch for transmitter 1. Latches QT alarms in Lower Memory,
Registers 72h–73h and 76h.
0 = QT alarm and warning flags reflect the status of the last comparison.
1 = QT alarm and warning flags remain set.
WLATCH1: ADC warning’s comparison latch for transmitter 1. Latches warnings in Lower Memory,
Registers 74h–75h.
0 = ADC warning flags reflect the status of the last comparison.
1 = ADC warning flags remain set.
INVOUT1
00h
PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
PW2 or (PW1 and RWTBL2)
Common A2h and B2h memory location
Nonvolatile (SEE)
ALATCH2
QTLATCH2
WLATCH2
ALATCH1
QTLATCH1
WLATCH1
BIT 0