X96012V14I Intersil, X96012V14I Datasheet - Page 21

• Manufacturer Part Number: X96012V14I
• Description: IC CNTRLR UNIV MEM/DAC 14-TSSOP
• Manufacturer: Intersil
• Type: Controllerr

Specifications of X96012V14I

• Input Type: *
• Output Type: *
• Interface: 2-Wire Serial
• Current - Supply: *
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The four registers Control 1 through 4, have a nonvolatile
and a volatile cell for each bit. At power-up, the content of
the nonvolatile cells is automatically recalled and written to
the volatile cells. The content of the volatile cells controls the
X96012’s functionality. If bit NV1234 in the Control 0 register
is set to “1”, a Write operation to these registers writes to
both the volatile and nonvolatile cells. If bit NV1234 in the
Control 0 register is set to “0”, a Write operation to these
registers only writes to the volatile cells. In both cases the
newly written values effectively control the X96012, but in
the second case, those values are lost when the part is
powered down.
If bit NV1234 is set to “0”, a Byte Write operation to Control
registers 0 or 5 causes the value in the nonvolatile cells of
Control registers 1 through 4 to be recalled into their
corresponding volatile cells, as during power-up. This
doesn’t happen when the WP pin is LOW, because Write
Protection is enabled. It is generally recommended to
configure Control registers 0 and 5 before writing to Control
registers 1 through 4.
When reading any of the control registers 1, 2, 3, or 4, the
Data Bytes are always the content of the corresponding
nonvolatile cells, even if bit NV1234 is "0". See “Control and
Status Registers” on page 9.
FROM THE
SIGNALS
MASTER
SIGNALS FROM
SIGNAL AT
THE SLAVE
SDA
SIGNAL AT SDA
SIGNALS FROM
SIGNALS FROM
THE MASTER
THE SLAVE
S
T
A
R
T
1
0
1
ADDRESS
R/W = 0
SLAVE
0
WITH
21
S
A
R
T
T
0
1
FIGURE 21. WRITING TO CONTROL REGISTERS 1, 2, 3 AND 4
0
A
C
K
ADDRESS
1
SLAVE
0
ADDRESS
BYTE
WRITE
0
FIGURE 22. READ SEQUENCE
A
C
K
1
0
BYTE = 81h
A
C
K
ADDRESS
0
S
A
R
T
T
X96012
0
1
0 0
0
ADDRESS
R/W = 1
1
SLAVE
0
WITH
0
1
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (see Figure 22). The master
initiates the operation issuing the following sequence: a
START, the Slave Address byte with the R/W bit set to “0”,
an Address Byte, a second START, and a second Slave
Address byte with the R/W bit set to “1”. After each of the
three bytes, the X96012 responds with an ACK. Then the
X96012 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eighth bit of each byte. The master terminates the read
operation (issuing a STOP condition) following the last bit of
the last Data Byte. See Figure 22.
The Data Bytes are from the memory location indicated by
an internal pointer. This pointer initial value is determined by
the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 10Fh the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
A Read operation internal pointer can start at any memory
location from 00h through FEh, when the Address Byte is
00h through FEh respectively. But it starts at location 100h if
the Address Byte is FFh.
When reading any of the control registers 1, 2, 3, or 4, the
Data Bytes are always the content of the corresponding
nonvolatile cells, even if bit NV1234 is "0". See “Control and
Status Registers” on page 9.
A
C
K
DATA BYTE FOR
CONTROL 1
1
A
C
K
FIRST READ
DATA BYTE
FOUR DATA BYTES
A
C
K
A
C
K
DATA BYTE FOR
CONTROL 4
A
C
K
LAST READ
DATA BYTE
A
C
K
O
S
T
P
February 20, 2008
FN8216.3
O
S
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