X96012V14I Intersil, X96012V14I Datasheet - Page 7

• Manufacturer Part Number: X96012V14I
• Description: IC CNTRLR UNIV MEM/DAC 14-TSSOP
• Manufacturer: Intersil
• Type: Controllerr

Specifications of X96012V14I

• Input Type: *
• Output Type: *
• Interface: 2-Wire Serial
• Current - Supply: *
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Nonvolatile WRITE Cycle Timing
NOTES:
16. Cb = total capacitance of one bus line (SDA or SCL) in pF.
17. t
18. The minimum frequency requirement applies between a START and a STOP condition.
t
Timing Diagrams
WC
SYMBOL
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
(Note 17)
WC
SDA OUT
SDA IN
is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
SCL
t
SU:STA
Nonvolatile Write Cycle Time
SDA IN
SCL
WP
PARAMETER
t
HD:STA
START
7
t
F
t
SU:DAT
t
SU:WP
t
HIGH
CLK 1
See Figure 3
FIGURE 2. WP PIN TIMING
FIGURE 1. BUS TIMING
t
TEST CONDITIONS
LOW
X96012
t
HD:DAT
t
R
t
HD:WP
t
AA
t
DH
(Note 3)
STOP
MIN
t
TYP
BUF
5
t
SU:STO
(Note 3)
MAX
10
February 20, 2008
UNITS
FN8216.3
ms